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Reland [SelectionDAG] Folding ZERO-EXTEND/SIGN_EXTEND poison to Poison value in getNode (#136701)
This patch addresses the signed/zero extension of poison by using a poison value of the extended type instead of a constant zero of the extended type.
1 parent 49b6c74 commit afda4c2

31 files changed

+129
-176
lines changed

Diff for: ‎llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

+8
Original file line numberDiff line numberDiff line change
@@ -6322,6 +6322,10 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
63226322
Flags.setNonNeg(N1->getFlags().hasNonNeg());
63236323
return getNode(OpOpcode, DL, VT, N1.getOperand(0), Flags);
63246324
}
6325+
6326+
if (OpOpcode == ISD::POISON)
6327+
return getPOISON(VT);
6328+
63256329
if (N1.isUndef())
63266330
// sext(undef) = 0, because the top bits will all be the same.
63276331
return getConstant(0, DL, VT);
@@ -6342,6 +6346,10 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
63426346
Flags.setNonNeg(N1->getFlags().hasNonNeg());
63436347
return getNode(ISD::ZERO_EXTEND, DL, VT, N1.getOperand(0), Flags);
63446348
}
6349+
6350+
if (OpOpcode == ISD::POISON)
6351+
return getPOISON(VT);
6352+
63456353
if (N1.isUndef())
63466354
// zext(undef) = 0, because the top bits will be zero.
63476355
return getConstant(0, DL, VT);

Diff for: ‎llvm/test/CodeGen/AArch64/arm64-bitfield-extract.ll

+1-1
Original file line numberDiff line numberDiff line change
@@ -1019,7 +1019,7 @@ define i16 @test_ignored_rightbits(i32 %dst, i32 %in) {
10191019
define void @sameOperandBFI(i64 %src, i64 %src2, ptr %ptr) {
10201020
; LLC-LABEL: sameOperandBFI:
10211021
; LLC: // %bb.0: // %entry
1022-
; LLC-NEXT: cbnz wzr, .LBB30_2
1022+
; LLC-NEXT: cbnz w8, .LBB30_2
10231023
; LLC-NEXT: // %bb.1: // %if.else
10241024
; LLC-NEXT: lsr x8, x0, #47
10251025
; LLC-NEXT: and w9, w1, #0x3

Diff for: ‎llvm/test/CodeGen/AArch64/optimize-cond-branch.ll

+1-1
Original file line numberDiff line numberDiff line change
@@ -16,7 +16,7 @@ define void @func() uwtable {
1616
; CHECK-NEXT: mov w8, #1 // =0x1
1717
; CHECK-NEXT: cbnz w8, .LBB0_3
1818
; CHECK-NEXT: // %bb.1: // %b1
19-
; CHECK-NEXT: cbz wzr, .LBB0_4
19+
; CHECK-NEXT: cbz w8, .LBB0_4
2020
; CHECK-NEXT: // %bb.2: // %b3
2121
; CHECK-NEXT: ldr w8, [x8]
2222
; CHECK-NEXT: and w0, w8, #0x100

Diff for: ‎llvm/test/CodeGen/AArch64/sve-extract-element.ll

-1
Original file line numberDiff line numberDiff line change
@@ -523,7 +523,6 @@ define double @test_lanex_2xf64(<vscale x 2 x double> %a, i32 %x) #0 {
523523
define i32 @test_undef_lane_4xi32(<vscale x 4 x i32> %a) #0 {
524524
; CHECK-LABEL: test_undef_lane_4xi32:
525525
; CHECK: // %bb.0:
526-
; CHECK-NEXT: fmov w0, s0
527526
; CHECK-NEXT: ret
528527
%b = extractelement <vscale x 4 x i32> %a, i32 poison
529528
ret i32 %b

Diff for: ‎llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.16bit.ll

+6-17
Original file line numberDiff line numberDiff line change
@@ -92,27 +92,17 @@ define i16 @bitcast_f16_to_i16(half %a, i32 %b) {
9292
; GCN-LABEL: bitcast_f16_to_i16:
9393
; GCN: ; %bb.0:
9494
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
95-
; GCN-NEXT: v_mov_b32_e32 v2, v0
96-
; GCN-NEXT: v_mov_b32_e32 v0, 0
9795
; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1
98-
; GCN-NEXT: v_cvt_f16_f32_e32 v1, v2
96+
; GCN-NEXT: v_cvt_f16_f32_e32 v0, v0
9997
; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc
10098
; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
101-
; GCN-NEXT: s_cbranch_execnz .LBB1_3
102-
; GCN-NEXT: ; %bb.1: ; %Flow
103-
; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
104-
; GCN-NEXT: s_cbranch_execnz .LBB1_4
105-
; GCN-NEXT: .LBB1_2: ; %end
106-
; GCN-NEXT: s_or_b64 exec, exec, s[4:5]
107-
; GCN-NEXT: s_setpc_b64 s[30:31]
108-
; GCN-NEXT: .LBB1_3: ; %cmp.false
109-
; GCN-NEXT: v_mov_b32_e32 v0, v1
11099
; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
111100
; GCN-NEXT: s_cbranch_execz .LBB1_2
112-
; GCN-NEXT: .LBB1_4: ; %cmp.true
113-
; GCN-NEXT: v_cvt_f32_f16_e32 v0, v1
101+
; GCN-NEXT: ; %bb.1:
102+
; GCN-NEXT: v_cvt_f32_f16_e32 v0, v0
114103
; GCN-NEXT: v_add_f32_e32 v0, 0x38000000, v0
115104
; GCN-NEXT: v_cvt_f16_f32_e32 v0, v0
105+
; GCN-NEXT: .LBB1_2:
116106
; GCN-NEXT: s_or_b64 exec, exec, s[4:5]
117107
; GCN-NEXT: s_setpc_b64 s[30:31]
118108
;
@@ -249,10 +239,9 @@ define i16 @bitcast_bf16_to_i16(bfloat %a, i32 %b) {
249239
; GCN-LABEL: bitcast_bf16_to_i16:
250240
; GCN: ; %bb.0:
251241
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
252-
; GCN-NEXT: v_mov_b32_e32 v2, v0
253-
; GCN-NEXT: v_mov_b32_e32 v0, 0
254242
; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1
255-
; GCN-NEXT: v_mul_f32_e32 v1, 1.0, v2
243+
; GCN-NEXT: v_mul_f32_e32 v1, 1.0, v0
244+
; GCN-NEXT: ; implicit-def: $vgpr0
256245
; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc
257246
; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
258247
; GCN-NEXT: s_cbranch_execnz .LBB3_3

Diff for: ‎llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll

+7-7
Original file line numberDiff line numberDiff line change
@@ -8383,10 +8383,10 @@ define amdgpu_kernel void @uniform_or_i16(ptr addrspace(1) %result, ptr addrspac
83838383
; GFX7LESS: ; %bb.0:
83848384
; GFX7LESS-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
83858385
; GFX7LESS-NEXT: s_load_dword s6, s[4:5], 0xd
8386-
; GFX7LESS-NEXT: v_mov_b32_e32 v0, 0
8387-
; GFX7LESS-NEXT: v_mbcnt_lo_u32_b32_e64 v1, exec_lo, 0
8388-
; GFX7LESS-NEXT: v_mbcnt_hi_u32_b32_e32 v1, exec_hi, v1
8389-
; GFX7LESS-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
8386+
; GFX7LESS-NEXT: v_mbcnt_lo_u32_b32_e64 v0, exec_lo, 0
8387+
; GFX7LESS-NEXT: v_mbcnt_hi_u32_b32_e32 v0, exec_hi, v0
8388+
; GFX7LESS-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
8389+
; GFX7LESS-NEXT: ; implicit-def: $vgpr0
83908390
; GFX7LESS-NEXT: s_and_saveexec_b64 s[4:5], vcc
83918391
; GFX7LESS-NEXT: s_cbranch_execz .LBB15_2
83928392
; GFX7LESS-NEXT: ; %bb.1:
@@ -8731,10 +8731,10 @@ define amdgpu_kernel void @uniform_add_i16(ptr addrspace(1) %result, ptr addrspa
87318731
; GFX7LESS-NEXT: s_mov_b64 s[6:7], exec
87328732
; GFX7LESS-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
87338733
; GFX7LESS-NEXT: s_load_dword s10, s[4:5], 0xd
8734-
; GFX7LESS-NEXT: v_mov_b32_e32 v0, 0
8735-
; GFX7LESS-NEXT: v_mbcnt_lo_u32_b32_e64 v1, s6, 0
8736-
; GFX7LESS-NEXT: v_mbcnt_hi_u32_b32_e32 v4, s7, v1
8734+
; GFX7LESS-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s6, 0
8735+
; GFX7LESS-NEXT: v_mbcnt_hi_u32_b32_e32 v4, s7, v0
87378736
; GFX7LESS-NEXT: v_cmp_eq_u32_e32 vcc, 0, v4
8737+
; GFX7LESS-NEXT: ; implicit-def: $vgpr0
87388738
; GFX7LESS-NEXT: s_and_saveexec_b64 s[8:9], vcc
87398739
; GFX7LESS-NEXT: s_cbranch_execz .LBB16_4
87408740
; GFX7LESS-NEXT: ; %bb.1:

Diff for: ‎llvm/test/CodeGen/AMDGPU/ctpop16.ll

+20-21
Original file line numberDiff line numberDiff line change
@@ -1292,7 +1292,7 @@ define amdgpu_kernel void @ctpop_i16_in_br(ptr addrspace(1) %out, ptr addrspace(
12921292
; SI-NEXT: buffer_store_short v0, off, s[0:3], 0
12931293
; SI-NEXT: s_endpgm
12941294
; SI-NEXT: .LBB14_4:
1295-
; SI-NEXT: v_mov_b32_e32 v0, 0
1295+
; SI-NEXT: ; implicit-def: $vgpr0
12961296
; SI-NEXT: s_branch .LBB14_2
12971297
;
12981298
; VI-LABEL: ctpop_i16_in_br:
@@ -1329,48 +1329,47 @@ define amdgpu_kernel void @ctpop_i16_in_br(ptr addrspace(1) %out, ptr addrspace(
13291329
; EG: ; %bb.0: ; %entry
13301330
; EG-NEXT: ALU 0, @20, KC0[], KC1[]
13311331
; EG-NEXT: TEX 0 @14
1332-
; EG-NEXT: ALU_PUSH_BEFORE 4, @21, KC0[], KC1[]
1332+
; EG-NEXT: ALU_PUSH_BEFORE 3, @21, KC0[], KC1[]
13331333
; EG-NEXT: JUMP @7 POP:1
1334-
; EG-NEXT: ALU 0, @26, KC0[CB0:0-32], KC1[]
1334+
; EG-NEXT: ALU 0, @25, KC0[CB0:0-32], KC1[]
13351335
; EG-NEXT: TEX 0 @16
1336-
; EG-NEXT: ALU_POP_AFTER 1, @27, KC0[], KC1[]
1337-
; EG-NEXT: ALU_PUSH_BEFORE 2, @29, KC0[CB0:0-32], KC1[]
1336+
; EG-NEXT: ALU_POP_AFTER 1, @26, KC0[], KC1[]
1337+
; EG-NEXT: ALU_PUSH_BEFORE 2, @28, KC0[CB0:0-32], KC1[]
13381338
; EG-NEXT: JUMP @11 POP:1
13391339
; EG-NEXT: TEX 0 @18
1340-
; EG-NEXT: ALU_POP_AFTER 0, @32, KC0[], KC1[]
1341-
; EG-NEXT: ALU 11, @33, KC0[], KC1[]
1340+
; EG-NEXT: ALU_POP_AFTER 0, @31, KC0[], KC1[]
1341+
; EG-NEXT: ALU 11, @32, KC0[], KC1[]
13421342
; EG-NEXT: MEM_RAT MSKOR T1.XW, T0.X
13431343
; EG-NEXT: CF_END
13441344
; EG-NEXT: Fetch clause starting at 14:
1345-
; EG-NEXT: VTX_READ_16 T2.X, T1.X, 46, #3
1345+
; EG-NEXT: VTX_READ_16 T1.X, T0.X, 46, #3
13461346
; EG-NEXT: Fetch clause starting at 16:
1347-
; EG-NEXT: VTX_READ_16 T0.X, T0.X, 2, #1
1347+
; EG-NEXT: VTX_READ_16 T1.X, T1.X, 2, #1
13481348
; EG-NEXT: Fetch clause starting at 18:
1349-
; EG-NEXT: VTX_READ_16 T0.X, T1.X, 44, #3
1349+
; EG-NEXT: VTX_READ_16 T0.X, T0.X, 44, #3
13501350
; EG-NEXT: ALU clause starting at 20:
1351-
; EG-NEXT: MOV * T1.X, 0.0,
1351+
; EG-NEXT: MOV * T0.X, 0.0,
13521352
; EG-NEXT: ALU clause starting at 21:
1353-
; EG-NEXT: MOV T0.X, literal.x,
1354-
; EG-NEXT: MOV T1.W, literal.y,
1355-
; EG-NEXT: SETNE_INT * T0.W, T2.X, 0.0,
1356-
; EG-NEXT: 0(0.000000e+00), 1(1.401298e-45)
1353+
; EG-NEXT: MOV T1.W, literal.x,
1354+
; EG-NEXT: SETNE_INT * T0.W, T1.X, 0.0,
1355+
; EG-NEXT: 1(1.401298e-45), 0(0.000000e+00)
13571356
; EG-NEXT: PRED_SETNE_INT * ExecMask,PredicateBit (MASKED), PS, 0.0,
1357+
; EG-NEXT: ALU clause starting at 25:
1358+
; EG-NEXT: MOV * T1.X, KC0[2].Z,
13581359
; EG-NEXT: ALU clause starting at 26:
1359-
; EG-NEXT: MOV * T0.X, KC0[2].Z,
1360-
; EG-NEXT: ALU clause starting at 27:
13611360
; EG-NEXT: MOV * T1.W, literal.x,
13621361
; EG-NEXT: 0(0.000000e+00), 0(0.000000e+00)
1363-
; EG-NEXT: ALU clause starting at 29:
1362+
; EG-NEXT: ALU clause starting at 28:
13641363
; EG-NEXT: MOV T0.W, KC0[2].Y,
13651364
; EG-NEXT: SETE_INT * T1.W, T1.W, 0.0,
13661365
; EG-NEXT: PRED_SETE_INT * ExecMask,PredicateBit (MASKED), PS, 0.0,
1366+
; EG-NEXT: ALU clause starting at 31:
1367+
; EG-NEXT: BCNT_INT * T1.X, T0.X,
13671368
; EG-NEXT: ALU clause starting at 32:
1368-
; EG-NEXT: BCNT_INT * T0.X, T0.X,
1369-
; EG-NEXT: ALU clause starting at 33:
13701369
; EG-NEXT: LSHL * T1.W, T0.W, literal.x,
13711370
; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)
13721371
; EG-NEXT: AND_INT T1.W, PV.W, literal.x,
1373-
; EG-NEXT: AND_INT * T2.W, T0.X, literal.y,
1372+
; EG-NEXT: AND_INT * T2.W, T1.X, literal.y,
13741373
; EG-NEXT: 24(3.363116e-44), 65535(9.183409e-41)
13751374
; EG-NEXT: LSHL T1.X, PS, PV.W,
13761375
; EG-NEXT: LSHL * T1.W, literal.x, PV.W,

Diff for: ‎llvm/test/CodeGen/AMDGPU/dead-machine-elim-after-dead-lane.ll

+5-4
Original file line numberDiff line numberDiff line change
@@ -6,15 +6,16 @@
66
define amdgpu_kernel void @foo() {
77
; CHECK-LABEL: foo:
88
; CHECK: ; %bb.0: ; %entry
9-
; CHECK-NEXT: s_cbranch_execnz .LBB0_2
10-
; CHECK-NEXT: ; %bb.1: ; %LeafBlock1
11-
; CHECK-NEXT: .LBB0_2: ; %foo.exit
9+
; CHECK-NEXT: ; %bb.1: ; %LeafBlock1
10+
; CHECK-NEXT: s_cmp_eq_u32 s0, 10
11+
; CHECK-NEXT: s_cbranch_scc1 .LBB0_3
12+
; CHECK-NEXT: ; %bb.2:
1213
; CHECK-NEXT: s_mov_b32 s3, 0xf000
1314
; CHECK-NEXT: s_mov_b32 s2, -1
1415
; CHECK-NEXT: v_mov_b32_e32 v0, 0
1516
; CHECK-NEXT: buffer_store_dword v0, off, s[0:3], 0
1617
; CHECK-NEXT: s_endpgm
17-
; CHECK-NEXT: ; %bb.3: ; %sw.bb10
18+
; CHECK-NEXT: .LBB0_3:
1819
entry:
1920
switch i8 poison, label %foo.exit [
2021
i8 4, label %sw.bb4

Diff for: ‎llvm/test/CodeGen/AMDGPU/mdt-preserving-crash.ll

+4-8
Original file line numberDiff line numberDiff line change
@@ -29,17 +29,13 @@ define protected amdgpu_kernel void @_RSENC_PRInit______________________________
2929
; CHECK-NEXT: s_cmp_eq_u32 s4, 0
3030
; CHECK-NEXT: s_cbranch_scc1 .LBB0_2
3131
; CHECK-NEXT: ; %bb.3: ; %if.end60
32-
; CHECK-NEXT: s_mov_b64 vcc, exec
3332
; CHECK-NEXT: s_cbranch_execz .LBB0_11
3433
; CHECK-NEXT: ; %bb.4: ; %if.end5.i
35-
; CHECK-NEXT: s_mov_b64 vcc, vcc
36-
; CHECK-NEXT: s_cbranch_vccz .LBB0_11
34+
; CHECK-NEXT: s_cbranch_scc0 .LBB0_11
3735
; CHECK-NEXT: ; %bb.5: ; %if.end5.i314
38-
; CHECK-NEXT: s_mov_b64 vcc, exec
39-
; CHECK-NEXT: s_cbranch_execz .LBB0_11
36+
; CHECK-NEXT: s_cbranch_scc0 .LBB0_11
4037
; CHECK-NEXT: ; %bb.6: ; %if.end5.i338
41-
; CHECK-NEXT: s_mov_b64 vcc, vcc
42-
; CHECK-NEXT: s_cbranch_vccz .LBB0_11
38+
; CHECK-NEXT: s_cbranch_scc0 .LBB0_11
4339
; CHECK-NEXT: ; %bb.7: ; %if.end5.i362
4440
; CHECK-NEXT: v_mov_b32_e32 v0, 0
4541
; CHECK-NEXT: s_getpc_b64 s[4:5]
@@ -50,7 +46,7 @@ define protected amdgpu_kernel void @_RSENC_PRInit______________________________
5046
; CHECK-NEXT: buffer_store_byte v0, v0, s[0:3], 0 offen
5147
; CHECK-NEXT: s_waitcnt vmcnt(1)
5248
; CHECK-NEXT: buffer_store_byte v1, off, s[0:3], 0 offset:257
53-
; CHECK-NEXT: s_cbranch_execz .LBB0_11
49+
; CHECK-NEXT: s_cbranch_scc0 .LBB0_11
5450
; CHECK-NEXT: ; %bb.8: ; %if.end5.i400
5551
; CHECK-NEXT: flat_load_ubyte v0, v[0:1]
5652
; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)

Diff for: ‎llvm/test/CodeGen/PowerPC/undef-args.ll

+8-9
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,7 @@
1-
;; Tests that extending poison results in undef.
2-
;; Also tests that there are redundant instructions loading 0 into argument registers for unused arguments.
1+
;; Tests that extending poison results in poison.
2+
;; Also tests that there are no redundant instructions loading 0 into argument registers for unused arguments.
3+
4+
; REQUIRES: asserts
35

46
; REQUIRES: asserts
57

@@ -62,7 +64,7 @@ entry:
6264
; CHECKISEL64-NEXT: t7: i64 = Register $x1
6365
; CHECKISEL64-NEXT: t0: ch,glue = EntryToken
6466
; CHECKISEL64-NEXT: t6: ch,glue = callseq_start t0, TargetConstant:i64<112>, TargetConstant:i64<0>
65-
; CHECKISEL64-NEXT: t11: ch,glue = CopyToReg t6, Register:i64 $x3, Constant:i64<0>
67+
; CHECKISEL64-NEXT: t11: ch,glue = CopyToReg t6, Register:i64 $x3, poison:i64
6668
; CHECKISEL64-NEXT: t13: ch,glue = CopyToReg t11, Register:i64 $x4, Constant:i64<255>, t11:1
6769
; CHECKISEL64-NEXT: t17: ch,glue = PPCISD::CALL_NOP t13, MCSymbol:i64, Register:i64 $x3, Register:i64 $x4, Register:i64 $x2, RegisterMask:Untyped, t13:1
6870
; CHECKISEL64-NEXT: t18: ch,glue = callseq_end t17, TargetConstant:i64<112>, TargetConstant:i64<0>, t17:1
@@ -72,7 +74,6 @@ entry:
7274
; CHECKASM64-NEXT: # %bb.0: # %entry
7375
; CHECKASM64-NEXT: mflr 0
7476
; CHECKASM64-NEXT: stdu 1, -112(1)
75-
; CHECKASM64-NEXT: li 3, 0
7677
; CHECKASM64-NEXT: li 4, 255
7778
; CHECKASM64-NEXT: std 0, 128(1)
7879
; CHECKASM64-NEXT: bl .bar32
@@ -104,7 +105,7 @@ entry:
104105
; CHECKISEL32-NEXT: t9: i32 = Register $r1
105106
; CHECKISEL32-NEXT: t0: ch,glue = EntryToken
106107
; CHECKISEL32-NEXT: t8: ch,glue = callseq_start t0, TargetConstant:i32<56>, TargetConstant:i32<0>
107-
; CHECKISEL32-NEXT: t11: ch,glue = CopyToReg t8, Register:i32 $r3, Constant:i32<0>
108+
; CHECKISEL32-NEXT: t11: ch,glue = CopyToReg t8, Register:i32 $r3, poison:i32
108109
; CHECKISEL32-NEXT: t13: ch,glue = CopyToReg t11, Register:i32 $r4, Constant:i32<255>, t11:1
109110
; CHECKISEL32-NEXT: t17: ch,glue = PPCISD::CALL_NOP t13, MCSymbol:i32, Register:i32 $r3, Register:i32 $r4, Register:i32 $r2, RegisterMask:Untyped, t13:1
110111
; CHECKISEL32-NEXT: t18: ch,glue = callseq_end t17, TargetConstant:i32<56>, TargetConstant:i32<0>, t17:1
@@ -114,7 +115,6 @@ entry:
114115
; CHECKASM32-NEXT: # %bb.0: # %entry
115116
; CHECKASM32-NEXT: mflr 0
116117
; CHECKASM32-NEXT: stwu 1, -64(1)
117-
; CHECKASM32-NEXT: li 3, 0
118118
; CHECKASM32-NEXT: li 4, 255
119119
; CHECKASM32-NEXT: stw 0, 72(1)
120120
; CHECKASM32-NEXT: bl .bar8
@@ -128,7 +128,6 @@ entry:
128128
; CHECKASM64-NEXT: # %bb.0: # %entry
129129
; CHECKASM64-NEXT: mflr 0
130130
; CHECKASM64-NEXT: stdu 1, -112(1)
131-
; CHECKASM64-NEXT: li 3, 0
132131
; CHECKASM64-NEXT: li 4, 255
133132
; CHECKASM64-NEXT: std 0, 128(1)
134133
; CHECKASM64-NEXT: bl .bar8
@@ -143,12 +142,12 @@ entry:
143142
; CHECKISEL64-NEXT: t1: i64 = GlobalAddress<ptr @bar8> 0
144143
; CHECKISEL64-NEXT: t2: i8 = poison
145144
; CHECKISEL64-NEXT: t3: i8 = Constant<-1>
146-
; CHECKISEL64-NEXT: t4: i32 = Constant<0>
145+
; CHECKISEL64-NEXT: t4: i32 = poison
147146
; CHECKISEL64-NEXT: t5: i32 = Constant<255>
148147
; CHECKISEL64-NEXT: t9: i64 = Register $x1
149148
; CHECKISEL64-NEXT: t0: ch,glue = EntryToken
150149
; CHECKISEL64-NEXT: t8: ch,glue = callseq_start t0, TargetConstant:i64<112>, TargetConstant:i64<0>
151-
; CHECKISEL64-NEXT: t13: ch,glue = CopyToReg t8, Register:i64 $x3, Constant:i64<0>
150+
; CHECKISEL64-NEXT: t13: ch,glue = CopyToReg t8, Register:i64 $x3, poison:i64
152151
; CHECKISEL64-NEXT: t15: ch,glue = CopyToReg t13, Register:i64 $x4, Constant:i64<255>, t13:1
153152
; CHECKISEL64-NEXT: t19: ch,glue = PPCISD::CALL_NOP t15, MCSymbol:i64, Register:i64 $x3, Register:i64 $x4, Register:i64 $x2, RegisterMask:Untyped, t15:1
154153
; CHECKISEL64-NEXT: t20: ch,glue = callseq_end t19, TargetConstant:i64<112>, TargetConstant:i64<0>, t19:1

Diff for: ‎llvm/test/CodeGen/RISCV/miss-sp-restore-eh.ll

-8
Original file line numberDiff line numberDiff line change
@@ -27,14 +27,6 @@ define signext i32 @foo() #1 personality ptr @__gxx_personality_v0 {
2727
; CHECK-NEXT: .cfi_remember_state
2828
; CHECK-NEXT: .Ltmp0:
2929
; CHECK-NEXT: addi sp, sp, -32
30-
; CHECK-NEXT: li a0, 0
31-
; CHECK-NEXT: li a1, 0
32-
; CHECK-NEXT: li a2, 0
33-
; CHECK-NEXT: li a3, 0
34-
; CHECK-NEXT: li a4, 0
35-
; CHECK-NEXT: li a5, 0
36-
; CHECK-NEXT: li a6, 0
37-
; CHECK-NEXT: li a7, 0
3830
; CHECK-NEXT: call _Z3fooiiiiiiiiiiPi
3931
; CHECK-NEXT: addi sp, sp, 32
4032
; CHECK-NEXT: .Ltmp1:

Diff for: ‎llvm/test/CodeGen/VE/Vector/ticket-64420.ll

+1
Original file line numberDiff line numberDiff line change
@@ -20,6 +20,7 @@
2020

2121
; SCALAR-LABEL: func:
2222
; SCALAR: # %bb.1:
23+
; SCALAR: or %s1, 0, (0)1
2324
; SCALAR-NEXT: st %s1, 8(, %s0)
2425
; SCALAR-NEXT: st %s1, (, %s0)
2526
; SCALAR-NEXT: b.l.t (, %s10)

Diff for: ‎llvm/test/CodeGen/X86/avx512-i1test.ll

+8-7
Original file line numberDiff line numberDiff line change
@@ -8,18 +8,19 @@ target triple = "x86_64-unknown-linux-gnu"
88
define void @func() {
99
; CHECK-LABEL: func:
1010
; CHECK: # %bb.0: # %bb1
11-
; CHECK-NEXT: xorl %eax, %eax
1211
; CHECK-NEXT: testb %al, %al
1312
; CHECK-NEXT: je .LBB0_1
1413
; CHECK-NEXT: # %bb.3: # %L_30
1514
; CHECK-NEXT: retq
16-
; CHECK-NEXT: .LBB0_1: # %bb56
17-
; CHECK-NEXT: xorl %eax, %eax
1815
; CHECK-NEXT: .p2align 4
19-
; CHECK-NEXT: .LBB0_2: # %bb33
20-
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
21-
; CHECK-NEXT: testb %al, %al
22-
; CHECK-NEXT: jmp .LBB0_2
16+
; CHECK-NEXT: .LBB0_1: # %bb33
17+
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
18+
; CHECK-NEXT: testb %al, %al
19+
; CHECK-NEXT: jne .LBB0_1
20+
; CHECK-NEXT: # %bb.2: # %bb35
21+
; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1
22+
; CHECK-NEXT: testb %al, %al
23+
; CHECK-NEXT: jmp .LBB0_1
2324
bb1:
2425
br i1 poison, label %L_10, label %L_10
2526

Diff for: ‎llvm/test/CodeGen/X86/bfloat.ll

-2
Original file line numberDiff line numberDiff line change
@@ -842,7 +842,6 @@ define <32 x bfloat> @pr63017_2() nounwind {
842842
;
843843
; SSE2-LABEL: pr63017_2:
844844
; SSE2: # %bb.0:
845-
; SSE2-NEXT: xorl %eax, %eax
846845
; SSE2-NEXT: testb %al, %al
847846
; SSE2-NEXT: jne .LBB16_1
848847
; SSE2-NEXT: # %bb.2: # %cond.load
@@ -1087,7 +1086,6 @@ define <32 x bfloat> @pr63017_2() nounwind {
10871086
; AVXNC-LABEL: pr63017_2:
10881087
; AVXNC: # %bb.0:
10891088
; AVXNC-NEXT: vbroadcastss {{.*#+}} ymm0 = [49024,49024,49024,49024,49024,49024,49024,49024,49024,49024,49024,49024,49024,49024,49024,49024]
1090-
; AVXNC-NEXT: xorl %eax, %eax
10911089
; AVXNC-NEXT: testb %al, %al
10921090
; AVXNC-NEXT: jne .LBB16_2
10931091
; AVXNC-NEXT: # %bb.1: # %cond.load

Diff for: ‎llvm/test/CodeGen/X86/clobber_frame_ptr.ll

-1
Original file line numberDiff line numberDiff line change
@@ -157,7 +157,6 @@ define ghccc void @test5() {
157157
; CHECK-NEXT: movq %rsp, %rbp
158158
; CHECK-NEXT: .cfi_def_cfa_register %rbp
159159
; CHECK-NEXT: andq $-8, %rsp
160-
; CHECK-NEXT: xorl %eax, %eax
161160
; CHECK-NEXT: testb %al, %al
162161
; CHECK-NEXT: jne .LBB3_2
163162
; CHECK-NEXT: # %bb.1: # %then

Diff for: ‎llvm/test/CodeGen/X86/concat-fpext-v2bf16.ll

-1
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,6 @@
44
define void @test(<2 x ptr> %ptr) {
55
; CHECK-LABEL: test:
66
; CHECK: # %bb.0: # %entry
7-
; CHECK-NEXT: xorl %eax, %eax
87
; CHECK-NEXT: testb %al, %al
98
; CHECK-NEXT: je .LBB0_1
109
; CHECK-NEXT: # %bb.2: # %loop.127.preheader

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