366
366
367
367
static const uint8_t default_regs[][2 ] = {
368
368
// OV7670 reference registers
369
- { CLKRC, OMV_OV7670_CLKRC },
369
+ { CLKRC, CLKRC_PRESCALER_BYPASS | OMV_OV7670_CLKRC },
370
370
{ TSLB, 0x04 },
371
371
{ COM7, 0x00 },
372
372
{ HSTART, 0x13 },
@@ -383,6 +383,7 @@ static const uint8_t default_regs[][2] = {
383
383
{ SCALING_DCWCTR, 0x11 },
384
384
{ SCALING_PCLK_DIV, 0xf0 },
385
385
{ SCALING_PCLK, 0x02 },
386
+ { COM10, COM10_VSYNC_NEG},
386
387
387
388
/* Gamma curve values */
388
389
{ SLOP, 0x20 },
@@ -557,7 +558,7 @@ static const uint8_t rgb565_regs[][2] = {
557
558
{ COM7, COM7_RGB_FMT }, /* Selects RGB mode */
558
559
{ RGB444, 0 }, /* No RGB444 please */
559
560
{ COM1, 0x0 }, /* CCIR601 */
560
- { COM15, COM15_FMT_RGB565 |COM15_OUT_00_FF},
561
+ { COM15, COM15_FMT_RGB565 | COM15_OUT_00_FF},
561
562
{ MVFP, MVFP_BLACK_SUN_EN },
562
563
{ COM9, 0x6A }, /* 128x gain ceiling; 0x8 is reserved bit */
563
564
{ MTX1, 0xb3 }, /* "matrix coefficient 1" */
@@ -591,16 +592,16 @@ static const uint8_t yuv422_regs[][2] = {
591
592
};
592
593
593
594
static const uint8_t vga_regs[][2 ] = {
594
- { COM3, COM3_DCW_EN },
595
- { COM14, 0x10 },
596
- { 0x72 , 0x22 }, // downsample by 4
597
- { 0x73 , 0xf2 }, // divide by 4
598
- { HSTART, 0x16 },
599
- { HSTOP, 0x04 },
600
- { HREF, 0xa4 },
601
- { VSTART, 0x22 },
595
+ { COM3, 0x00 },
596
+ { COM14, 0x00 },
597
+ { 0x72 , 0x11 }, // downsample by 4
598
+ { 0x73 , 0xf0 }, // divide by 4
599
+ { HSTART, 0x12 },
600
+ { HSTOP, 0x00 },
601
+ { HREF, 0xb6 },
602
+ { VSTART, 0x02 },
602
603
{ VSTOP, 0x7a },
603
- { VREF, 0x0a },
604
+ { VREF, 0x00 },
604
605
{ 0xFF , 0xFF },
605
606
};
606
607
@@ -620,12 +621,11 @@ static const uint8_t qvga_regs[][2] = {
620
621
};
621
622
#else
622
623
static const uint8_t qvga_regs[][2 ] = {
623
- // { COM7, COM7_RES_QVGA },
624
624
{ COM3, COM3_DCW_EN },
625
- { COM14, 0x1a },
626
- { 0x72 , 0x22 }, // downsample by 4
627
- { 0x73 , 0xf2 }, // divide by 4
628
- { HSTART, 0x16 },
625
+ { COM14, 0x19 },
626
+ { 0x72 , 0x11 }, // downsample by 2
627
+ { 0x73 , 0xf1 }, // divide by 2
628
+ { HSTART, 0x15 },
629
629
{ HSTOP, 0x04 },
630
630
{ HREF, 0xa4 },
631
631
{ VSTART, 0x02 },
@@ -638,15 +638,15 @@ static const uint8_t qvga_regs[][2] = {
638
638
#if (OMV_OV7670_VERSION == 75)
639
639
static const uint8_t qqvga_regs[][2 ] = {
640
640
{ COM3, COM3_DCW_EN },
641
- { COM14, 0x12 }, // Divide by 4
641
+ { COM14, 0x11 }, // Divide by 2
642
642
{ 0x72 , 0x22 }, // This has no effect on OV7675
643
643
{ 0x73 , 0xf2 }, // This has no effect on OV7675
644
644
{ HSTART, 0x16 },
645
645
{ HSTOP, 0x04 },
646
646
{ HREF, 0xa4 },
647
647
{ VSTART, 0x22 },
648
648
{ VSTOP, 0x7a },
649
- { VREF, 0xFa },
649
+ { VREF, 0xfa },
650
650
{ 0xFF , 0xFF },
651
651
};
652
652
#else
@@ -678,14 +678,12 @@ int OV7670::init()
678
678
int ret = 0 ;
679
679
reset ();
680
680
681
- delay (10 );
682
-
683
681
// Write default registers
684
- for (int i = 0 ; default_regs[i][0 ]; i++) {
682
+ for (int i = 0 ; default_regs[i][0 ] != 0xFF ; i++) {
685
683
ret |= regWrite (getID (), default_regs[i][0 ], default_regs[i][1 ]);
686
684
}
687
685
688
- // regWrite(getID(), COM10, COM10_PCLK_MASK );
686
+ delay ( 300 );
689
687
690
688
return ret;
691
689
}
@@ -697,7 +695,9 @@ int OV7670::setWindow(uint16_t reg, uint16_t x, uint16_t y, uint16_t w, uint16_t
697
695
698
696
int OV7670::reset ()
699
697
{
700
- return regWrite (getID (), COM7, COM7_RESET);
698
+ int ret = regWrite (getID (), COM7, COM7_RESET);
699
+ delay (10 );
700
+ return ret;
701
701
}
702
702
703
703
int OV7670::setFrameRate (int32_t framerate)
0 commit comments