Use ISB as a spin-delay instruction on ARM64.

This seems beneficial on high-core-count machines, and not harmful
on lesser hardware.  However, older ARM32 gear doesn't have this
instruction, so restrict the patch to ARM64.

Geoffrey Blake

Discussion: https://postgr.es/m/78338F29-9D7F-4DC8-BD71-E9674CE71425@amazon.com

diff --git a/src/include/storage/s_lock.h b/src/include/storage/s_lock.h
index 8a5a905e380961c459e2114f4fefa8e13dda4d9c..af1145d98f6906448c5f78224bb66dd67b6c213e 100644 (file)
--- a/src/include/storage/s_lock.h
+++ b/src/include/storage/s_lock.h
@@ -337,6 +337,23 @@ tas(volatile slock_t *lock)
 
 #define S_UNLOCK(lock) __sync_lock_release(lock)
 
+/*
+ * Using an ISB instruction to delay in spinlock loops appears beneficial on
+ * high-core-count ARM64 processors.  It seems mostly a wash for smaller gear,
+ * and ISB doesn't exist at all on pre-v7 ARM chips.
+ */
+#if defined(__aarch64__) || defined(__aarch64)
+
+#define SPIN_DELAY() spin_delay()
+
+static __inline__ void
+spin_delay(void)
+{
+   __asm__ __volatile__(
+       " isb;              \n");
+}
+
+#endif  /* __aarch64__ || __aarch64 */
 #endif  /* HAVE_GCC__SYNC_INT32_TAS */
 #endif  /* __arm__ || __arm || __aarch64__ || __aarch64 */