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guanucoluis opened this issue Oct 8, 2020 · 1 comment
Closed

problem to make the project #2

guanucoluis opened this issue Oct 8, 2020 · 1 comment

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@guanucoluis
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Hello,
I cloned the project but I had problem when i ran make run...

(base) lguanuco@latitude:github$ git clone https://github.com/verilator/example-systemverilog.git
(base) lguanuco@latitude:github$ cd example-systemverilog/
(base) lguanuco@latitude:example-systemverilog$ make run

-- Verilator coverage example

-- VERILATE ----------------
verilator -cc --exe -Os -x-assign 0 -Wall --assert --coverage --build -j -f input.vc top.v sim_main.cpp
%Error: Invalid Option: --build
%Error: Command Failed /usr/bin/verilator_bin -cc --exe -Os -x-assign 0 -Wall --assert --coverage --build -j -f input.vc top.v sim_main.cpp
Makefile:79: fallo en las instrucciones para el objetivo 'run'
make: *** [run] Error 10

(base) lguanuco@latitude:example-systemverilog$ verilator --version
Verilator 3.900 2017-01-15 rev verilator_3_890-15-ge6d7e7e

I tried run the script without --build -j flags but I'm still having problems...

(base) lguanuco@latitude:example-systemverilog$ make run

-- Verilator coverage example

-- VERILATE ----------------
verilator -cc --exe -Os -x-assign 0 -Wall --assert --coverage -f input.vc top.v sim_main.cpp
%Warning-UNUSED: top.v:9: Signal is not driven, nor used: __Vtogcov__clk
%Warning-UNUSED: Use "/* verilator lint_off UNUSED */" and lint_on around source to disable this message.
%Warning-UNUSED: top.v:10: Signal is not driven, nor used: __Vtogcov__reset
%Warning-UNUSED: top.v:13: Signal is not driven, nor used: __Vtogcov__count_c
%Warning-UNUSED: top.v:33: Signal is not driven, nor used: __Vtogcov__count_hit_50
%Warning-UNUSED: top.v:34: Signal is not driven, nor used: __Vtogcov__count_hit_500
%Error: Exiting due to 5 warning(s)
%Error: Command Failed /usr/bin/verilator_bin -cc --exe -Os -x-assign 0 -Wall --assert --coverage -f input.vc top.v sim_main.cpp
Makefile:79: fallo en las instrucciones para el objetivo 'run'
make: *** [run] Error 10

I didn't find more information about this example. I want to apply the verilator coverage feature to my systemverilog project.
Regards,
Luis.

@wsnyder
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wsnyder commented Oct 8, 2020

It looks like you are using an old version of verilator, please use at least 4.038, ideally the current stable release 4.100.

Closing as think this will solve it, but feel free to post more here.

@wsnyder wsnyder closed this as completed Oct 8, 2020
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