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I tried run the script without --build -j flags but I'm still having problems...
(base) lguanuco@latitude:example-systemverilog$ make run
-- Verilator coverage example
-- VERILATE ----------------
verilator -cc --exe -Os -x-assign 0 -Wall --assert --coverage -f input.vc top.v sim_main.cpp
%Warning-UNUSED: top.v:9: Signal is not driven, nor used: __Vtogcov__clk
%Warning-UNUSED: Use "/* verilator lint_off UNUSED */" and lint_on around source to disable this message.
%Warning-UNUSED: top.v:10: Signal is not driven, nor used: __Vtogcov__reset
%Warning-UNUSED: top.v:13: Signal is not driven, nor used: __Vtogcov__count_c
%Warning-UNUSED: top.v:33: Signal is not driven, nor used: __Vtogcov__count_hit_50
%Warning-UNUSED: top.v:34: Signal is not driven, nor used: __Vtogcov__count_hit_500
%Error: Exiting due to 5 warning(s)
%Error: Command Failed /usr/bin/verilator_bin -cc --exe -Os -x-assign 0 -Wall --assert --coverage -f input.vc top.v sim_main.cpp
Makefile:79: fallo en las instrucciones para el objetivo 'run'
make: *** [run] Error 10
I didn't find more information about this example. I want to apply the verilator coverage feature to my systemverilog project.
Regards,
Luis.
The text was updated successfully, but these errors were encountered:
Hello,
I cloned the project but I had problem when i ran
make run
...(base) lguanuco@latitude:github$ git clone https://github.com/verilator/example-systemverilog.git
(base) lguanuco@latitude:github$ cd example-systemverilog/
(base) lguanuco@latitude:example-systemverilog$ make run
-- Verilator coverage example
-- VERILATE ----------------
verilator -cc --exe -Os -x-assign 0 -Wall --assert --coverage --build -j -f input.vc top.v sim_main.cpp
%Error: Invalid Option: --build
%Error: Command Failed /usr/bin/verilator_bin -cc --exe -Os -x-assign 0 -Wall --assert --coverage --build -j -f input.vc top.v sim_main.cpp
Makefile:79: fallo en las instrucciones para el objetivo 'run'
make: *** [run] Error 10
(base) lguanuco@latitude:example-systemverilog$ verilator --version
Verilator 3.900 2017-01-15 rev verilator_3_890-15-ge6d7e7e
I tried run the script without
--build -j
flags but I'm still having problems...(base) lguanuco@latitude:example-systemverilog$ make run
-- Verilator coverage example
-- VERILATE ----------------
verilator -cc --exe -Os -x-assign 0 -Wall --assert --coverage -f input.vc top.v sim_main.cpp
%Warning-UNUSED: top.v:9: Signal is not driven, nor used: __Vtogcov__clk
%Warning-UNUSED: Use "/* verilator lint_off UNUSED */" and lint_on around source to disable this message.
%Warning-UNUSED: top.v:10: Signal is not driven, nor used: __Vtogcov__reset
%Warning-UNUSED: top.v:13: Signal is not driven, nor used: __Vtogcov__count_c
%Warning-UNUSED: top.v:33: Signal is not driven, nor used: __Vtogcov__count_hit_50
%Warning-UNUSED: top.v:34: Signal is not driven, nor used: __Vtogcov__count_hit_500
%Error: Exiting due to 5 warning(s)
%Error: Command Failed /usr/bin/verilator_bin -cc --exe -Os -x-assign 0 -Wall --assert --coverage -f input.vc top.v sim_main.cpp
Makefile:79: fallo en las instrucciones para el objetivo 'run'
make: *** [run] Error 10
I didn't find more information about this example. I want to apply the verilator coverage feature to my systemverilog project.
Regards,
Luis.
The text was updated successfully, but these errors were encountered: