-
Notifications
You must be signed in to change notification settings - Fork 16
/
Copy pathstm32f429x-rcc.ads
1808 lines (1715 loc) · 72.8 KB
/
stm32f429x-rcc.ads
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
pragma Style_Checks (Off);
-- This spec has been automatically generated from STM32F429x.svd
pragma Restrictions (No_Elaboration_Code);
with System;
package STM32F429x.RCC is
pragma Preelaborate;
---------------
-- Registers --
---------------
subtype CR_HSION_Field is STM32F429x.Bit;
subtype CR_HSIRDY_Field is STM32F429x.Bit;
subtype CR_HSITRIM_Field is STM32F429x.UInt5;
subtype CR_HSICAL_Field is STM32F429x.Byte;
subtype CR_HSEON_Field is STM32F429x.Bit;
subtype CR_HSERDY_Field is STM32F429x.Bit;
subtype CR_HSEBYP_Field is STM32F429x.Bit;
subtype CR_CSSON_Field is STM32F429x.Bit;
subtype CR_PLLON_Field is STM32F429x.Bit;
subtype CR_PLLRDY_Field is STM32F429x.Bit;
subtype CR_PLLI2SON_Field is STM32F429x.Bit;
subtype CR_PLLI2SRDY_Field is STM32F429x.Bit;
-- clock control register
type CR_Register is record
-- Internal high-speed clock enable
HSION : CR_HSION_Field := 16#1#;
-- Read-only. Internal high-speed clock ready flag
HSIRDY : CR_HSIRDY_Field := 16#1#;
-- unspecified
Reserved_2_2 : STM32F429x.Bit := 16#0#;
-- Internal high-speed clock trimming
HSITRIM : CR_HSITRIM_Field := 16#10#;
-- Read-only. Internal high-speed clock calibration
HSICAL : CR_HSICAL_Field := 16#0#;
-- HSE clock enable
HSEON : CR_HSEON_Field := 16#0#;
-- Read-only. HSE clock ready flag
HSERDY : CR_HSERDY_Field := 16#0#;
-- HSE clock bypass
HSEBYP : CR_HSEBYP_Field := 16#0#;
-- Clock security system enable
CSSON : CR_CSSON_Field := 16#0#;
-- unspecified
Reserved_20_23 : STM32F429x.UInt4 := 16#0#;
-- Main PLL (PLL) enable
PLLON : CR_PLLON_Field := 16#0#;
-- Read-only. Main PLL (PLL) clock ready flag
PLLRDY : CR_PLLRDY_Field := 16#0#;
-- PLLI2S enable
PLLI2SON : CR_PLLI2SON_Field := 16#0#;
-- Read-only. PLLI2S clock ready flag
PLLI2SRDY : CR_PLLI2SRDY_Field := 16#0#;
-- unspecified
Reserved_28_31 : STM32F429x.UInt4 := 16#0#;
end record
with Object_Size => 32, Bit_Order => System.Low_Order_First;
for CR_Register use record
HSION at 0 range 0 .. 0;
HSIRDY at 0 range 1 .. 1;
Reserved_2_2 at 0 range 2 .. 2;
HSITRIM at 0 range 3 .. 7;
HSICAL at 0 range 8 .. 15;
HSEON at 0 range 16 .. 16;
HSERDY at 0 range 17 .. 17;
HSEBYP at 0 range 18 .. 18;
CSSON at 0 range 19 .. 19;
Reserved_20_23 at 0 range 20 .. 23;
PLLON at 0 range 24 .. 24;
PLLRDY at 0 range 25 .. 25;
PLLI2SON at 0 range 26 .. 26;
PLLI2SRDY at 0 range 27 .. 27;
Reserved_28_31 at 0 range 28 .. 31;
end record;
subtype PLLCFGR_PLLM_Field is STM32F429x.UInt6;
subtype PLLCFGR_PLLN_Field is STM32F429x.UInt9;
subtype PLLCFGR_PLLP_Field is STM32F429x.UInt2;
subtype PLLCFGR_PLLSRC_Field is STM32F429x.Bit;
subtype PLLCFGR_PLLQ_Field is STM32F429x.UInt4;
-- PLL configuration register
type PLLCFGR_Register is record
-- Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input
-- clock
PLLM : PLLCFGR_PLLM_Field := 16#10#;
-- Main PLL (PLL) multiplication factor for VCO
PLLN : PLLCFGR_PLLN_Field := 16#C0#;
-- unspecified
Reserved_15_15 : STM32F429x.Bit := 16#0#;
-- Main PLL (PLL) division factor for main system clock
PLLP : PLLCFGR_PLLP_Field := 16#0#;
-- unspecified
Reserved_18_21 : STM32F429x.UInt4 := 16#0#;
-- Main PLL(PLL) and audio PLL (PLLI2S) entry clock source
PLLSRC : PLLCFGR_PLLSRC_Field := 16#0#;
-- unspecified
Reserved_23_23 : STM32F429x.Bit := 16#0#;
-- Main PLL (PLL) division factor for USB OTG FS, SDIO and random number
-- generator clocks
PLLQ : PLLCFGR_PLLQ_Field := 16#4#;
-- unspecified
Reserved_28_31 : STM32F429x.UInt4 := 16#2#;
end record
with Object_Size => 32, Bit_Order => System.Low_Order_First;
for PLLCFGR_Register use record
PLLM at 0 range 0 .. 5;
PLLN at 0 range 6 .. 14;
Reserved_15_15 at 0 range 15 .. 15;
PLLP at 0 range 16 .. 17;
Reserved_18_21 at 0 range 18 .. 21;
PLLSRC at 0 range 22 .. 22;
Reserved_23_23 at 0 range 23 .. 23;
PLLQ at 0 range 24 .. 27;
Reserved_28_31 at 0 range 28 .. 31;
end record;
subtype CFGR_SW_Field is STM32F429x.UInt2;
subtype CFGR_SWS_Field is STM32F429x.UInt2;
subtype CFGR_HPRE_Field is STM32F429x.UInt4;
-- CFGR_PPRE array element
subtype CFGR_PPRE_Element is STM32F429x.UInt3;
-- CFGR_PPRE array
type CFGR_PPRE_Field_Array is array (1 .. 2) of CFGR_PPRE_Element
with Component_Size => 3, Size => 6;
-- Type definition for CFGR_PPRE
type CFGR_PPRE_Field
(As_Array : Boolean := False)
is record
case As_Array is
when False =>
-- PPRE as a value
Val : STM32F429x.UInt6;
when True =>
-- PPRE as an array
Arr : CFGR_PPRE_Field_Array;
end case;
end record
with Unchecked_Union, Size => 6;
for CFGR_PPRE_Field use record
Val at 0 range 0 .. 5;
Arr at 0 range 0 .. 5;
end record;
subtype CFGR_RTCPRE_Field is STM32F429x.UInt5;
subtype CFGR_MCO1_Field is STM32F429x.UInt2;
subtype CFGR_I2SSRC_Field is STM32F429x.Bit;
subtype CFGR_MCO1PRE_Field is STM32F429x.UInt3;
subtype CFGR_MCO2PRE_Field is STM32F429x.UInt3;
subtype CFGR_MCO2_Field is STM32F429x.UInt2;
-- clock configuration register
type CFGR_Register is record
-- System clock switch
SW : CFGR_SW_Field := 16#0#;
-- Read-only. System clock switch status
SWS : CFGR_SWS_Field := 16#0#;
-- AHB prescaler
HPRE : CFGR_HPRE_Field := 16#0#;
-- unspecified
Reserved_8_9 : STM32F429x.UInt2 := 16#0#;
-- APB Low speed prescaler (APB1)
PPRE : CFGR_PPRE_Field := (As_Array => False, Val => 16#0#);
-- HSE division factor for RTC clock
RTCPRE : CFGR_RTCPRE_Field := 16#0#;
-- Microcontroller clock output 1
MCO1 : CFGR_MCO1_Field := 16#0#;
-- I2S clock selection
I2SSRC : CFGR_I2SSRC_Field := 16#0#;
-- MCO1 prescaler
MCO1PRE : CFGR_MCO1PRE_Field := 16#0#;
-- MCO2 prescaler
MCO2PRE : CFGR_MCO2PRE_Field := 16#0#;
-- Microcontroller clock output 2
MCO2 : CFGR_MCO2_Field := 16#0#;
end record
with Object_Size => 32, Bit_Order => System.Low_Order_First;
for CFGR_Register use record
SW at 0 range 0 .. 1;
SWS at 0 range 2 .. 3;
HPRE at 0 range 4 .. 7;
Reserved_8_9 at 0 range 8 .. 9;
PPRE at 0 range 10 .. 15;
RTCPRE at 0 range 16 .. 20;
MCO1 at 0 range 21 .. 22;
I2SSRC at 0 range 23 .. 23;
MCO1PRE at 0 range 24 .. 26;
MCO2PRE at 0 range 27 .. 29;
MCO2 at 0 range 30 .. 31;
end record;
subtype CIR_LSIRDYF_Field is STM32F429x.Bit;
subtype CIR_LSERDYF_Field is STM32F429x.Bit;
subtype CIR_HSIRDYF_Field is STM32F429x.Bit;
subtype CIR_HSERDYF_Field is STM32F429x.Bit;
subtype CIR_PLLRDYF_Field is STM32F429x.Bit;
subtype CIR_PLLI2SRDYF_Field is STM32F429x.Bit;
subtype CIR_PLLSAIRDYF_Field is STM32F429x.Bit;
subtype CIR_CSSF_Field is STM32F429x.Bit;
subtype CIR_LSIRDYIE_Field is STM32F429x.Bit;
subtype CIR_LSERDYIE_Field is STM32F429x.Bit;
subtype CIR_HSIRDYIE_Field is STM32F429x.Bit;
subtype CIR_HSERDYIE_Field is STM32F429x.Bit;
subtype CIR_PLLRDYIE_Field is STM32F429x.Bit;
subtype CIR_PLLI2SRDYIE_Field is STM32F429x.Bit;
subtype CIR_PLLSAIRDYIE_Field is STM32F429x.Bit;
subtype CIR_LSIRDYC_Field is STM32F429x.Bit;
subtype CIR_LSERDYC_Field is STM32F429x.Bit;
subtype CIR_HSIRDYC_Field is STM32F429x.Bit;
subtype CIR_HSERDYC_Field is STM32F429x.Bit;
subtype CIR_PLLRDYC_Field is STM32F429x.Bit;
subtype CIR_PLLI2SRDYC_Field is STM32F429x.Bit;
subtype CIR_PLLSAIRDYC_Field is STM32F429x.Bit;
subtype CIR_CSSC_Field is STM32F429x.Bit;
-- clock interrupt register
type CIR_Register is record
-- Read-only. LSI ready interrupt flag
LSIRDYF : CIR_LSIRDYF_Field := 16#0#;
-- Read-only. LSE ready interrupt flag
LSERDYF : CIR_LSERDYF_Field := 16#0#;
-- Read-only. HSI ready interrupt flag
HSIRDYF : CIR_HSIRDYF_Field := 16#0#;
-- Read-only. HSE ready interrupt flag
HSERDYF : CIR_HSERDYF_Field := 16#0#;
-- Read-only. Main PLL (PLL) ready interrupt flag
PLLRDYF : CIR_PLLRDYF_Field := 16#0#;
-- Read-only. PLLI2S ready interrupt flag
PLLI2SRDYF : CIR_PLLI2SRDYF_Field := 16#0#;
-- Read-only. PLLSAI ready interrupt flag
PLLSAIRDYF : CIR_PLLSAIRDYF_Field := 16#0#;
-- Read-only. Clock security system interrupt flag
CSSF : CIR_CSSF_Field := 16#0#;
-- LSI ready interrupt enable
LSIRDYIE : CIR_LSIRDYIE_Field := 16#0#;
-- LSE ready interrupt enable
LSERDYIE : CIR_LSERDYIE_Field := 16#0#;
-- HSI ready interrupt enable
HSIRDYIE : CIR_HSIRDYIE_Field := 16#0#;
-- HSE ready interrupt enable
HSERDYIE : CIR_HSERDYIE_Field := 16#0#;
-- Main PLL (PLL) ready interrupt enable
PLLRDYIE : CIR_PLLRDYIE_Field := 16#0#;
-- PLLI2S ready interrupt enable
PLLI2SRDYIE : CIR_PLLI2SRDYIE_Field := 16#0#;
-- PLLSAI Ready Interrupt Enable
PLLSAIRDYIE : CIR_PLLSAIRDYIE_Field := 16#0#;
-- unspecified
Reserved_15_15 : STM32F429x.Bit := 16#0#;
-- Write-only. LSI ready interrupt clear
LSIRDYC : CIR_LSIRDYC_Field := 16#0#;
-- Write-only. LSE ready interrupt clear
LSERDYC : CIR_LSERDYC_Field := 16#0#;
-- Write-only. HSI ready interrupt clear
HSIRDYC : CIR_HSIRDYC_Field := 16#0#;
-- Write-only. HSE ready interrupt clear
HSERDYC : CIR_HSERDYC_Field := 16#0#;
-- Write-only. Main PLL(PLL) ready interrupt clear
PLLRDYC : CIR_PLLRDYC_Field := 16#0#;
-- Write-only. PLLI2S ready interrupt clear
PLLI2SRDYC : CIR_PLLI2SRDYC_Field := 16#0#;
-- Write-only. PLLSAI Ready Interrupt Clear
PLLSAIRDYC : CIR_PLLSAIRDYC_Field := 16#0#;
-- Write-only. Clock security system interrupt clear
CSSC : CIR_CSSC_Field := 16#0#;
-- unspecified
Reserved_24_31 : STM32F429x.Byte := 16#0#;
end record
with Object_Size => 32, Bit_Order => System.Low_Order_First;
for CIR_Register use record
LSIRDYF at 0 range 0 .. 0;
LSERDYF at 0 range 1 .. 1;
HSIRDYF at 0 range 2 .. 2;
HSERDYF at 0 range 3 .. 3;
PLLRDYF at 0 range 4 .. 4;
PLLI2SRDYF at 0 range 5 .. 5;
PLLSAIRDYF at 0 range 6 .. 6;
CSSF at 0 range 7 .. 7;
LSIRDYIE at 0 range 8 .. 8;
LSERDYIE at 0 range 9 .. 9;
HSIRDYIE at 0 range 10 .. 10;
HSERDYIE at 0 range 11 .. 11;
PLLRDYIE at 0 range 12 .. 12;
PLLI2SRDYIE at 0 range 13 .. 13;
PLLSAIRDYIE at 0 range 14 .. 14;
Reserved_15_15 at 0 range 15 .. 15;
LSIRDYC at 0 range 16 .. 16;
LSERDYC at 0 range 17 .. 17;
HSIRDYC at 0 range 18 .. 18;
HSERDYC at 0 range 19 .. 19;
PLLRDYC at 0 range 20 .. 20;
PLLI2SRDYC at 0 range 21 .. 21;
PLLSAIRDYC at 0 range 22 .. 22;
CSSC at 0 range 23 .. 23;
Reserved_24_31 at 0 range 24 .. 31;
end record;
subtype AHB1RSTR_GPIOARST_Field is STM32F429x.Bit;
subtype AHB1RSTR_GPIOBRST_Field is STM32F429x.Bit;
subtype AHB1RSTR_GPIOCRST_Field is STM32F429x.Bit;
subtype AHB1RSTR_GPIODRST_Field is STM32F429x.Bit;
subtype AHB1RSTR_GPIOERST_Field is STM32F429x.Bit;
subtype AHB1RSTR_GPIOFRST_Field is STM32F429x.Bit;
subtype AHB1RSTR_GPIOGRST_Field is STM32F429x.Bit;
subtype AHB1RSTR_GPIOHRST_Field is STM32F429x.Bit;
subtype AHB1RSTR_GPIOIRST_Field is STM32F429x.Bit;
subtype AHB1RSTR_GPIOJRST_Field is STM32F429x.Bit;
subtype AHB1RSTR_GPIOKRST_Field is STM32F429x.Bit;
subtype AHB1RSTR_CRCRST_Field is STM32F429x.Bit;
subtype AHB1RSTR_DMA1RST_Field is STM32F429x.Bit;
subtype AHB1RSTR_DMA2RST_Field is STM32F429x.Bit;
subtype AHB1RSTR_DMA2DRST_Field is STM32F429x.Bit;
subtype AHB1RSTR_ETHMACRST_Field is STM32F429x.Bit;
subtype AHB1RSTR_OTGHSRST_Field is STM32F429x.Bit;
-- AHB1 peripheral reset register
type AHB1RSTR_Register is record
-- IO port A reset
GPIOARST : AHB1RSTR_GPIOARST_Field := 16#0#;
-- IO port B reset
GPIOBRST : AHB1RSTR_GPIOBRST_Field := 16#0#;
-- IO port C reset
GPIOCRST : AHB1RSTR_GPIOCRST_Field := 16#0#;
-- IO port D reset
GPIODRST : AHB1RSTR_GPIODRST_Field := 16#0#;
-- IO port E reset
GPIOERST : AHB1RSTR_GPIOERST_Field := 16#0#;
-- IO port F reset
GPIOFRST : AHB1RSTR_GPIOFRST_Field := 16#0#;
-- IO port G reset
GPIOGRST : AHB1RSTR_GPIOGRST_Field := 16#0#;
-- IO port H reset
GPIOHRST : AHB1RSTR_GPIOHRST_Field := 16#0#;
-- IO port I reset
GPIOIRST : AHB1RSTR_GPIOIRST_Field := 16#0#;
-- IO port J reset
GPIOJRST : AHB1RSTR_GPIOJRST_Field := 16#0#;
-- IO port K reset
GPIOKRST : AHB1RSTR_GPIOKRST_Field := 16#0#;
-- unspecified
Reserved_11_11 : STM32F429x.Bit := 16#0#;
-- CRC reset
CRCRST : AHB1RSTR_CRCRST_Field := 16#0#;
-- unspecified
Reserved_13_20 : STM32F429x.Byte := 16#0#;
-- DMA2 reset
DMA1RST : AHB1RSTR_DMA1RST_Field := 16#0#;
-- DMA2 reset
DMA2RST : AHB1RSTR_DMA2RST_Field := 16#0#;
-- DMA2D reset
DMA2DRST : AHB1RSTR_DMA2DRST_Field := 16#0#;
-- unspecified
Reserved_24_24 : STM32F429x.Bit := 16#0#;
-- Ethernet MAC reset
ETHMACRST : AHB1RSTR_ETHMACRST_Field := 16#0#;
-- unspecified
Reserved_26_28 : STM32F429x.UInt3 := 16#0#;
-- USB OTG HS module reset
OTGHSRST : AHB1RSTR_OTGHSRST_Field := 16#0#;
-- unspecified
Reserved_30_31 : STM32F429x.UInt2 := 16#0#;
end record
with Object_Size => 32, Bit_Order => System.Low_Order_First;
for AHB1RSTR_Register use record
GPIOARST at 0 range 0 .. 0;
GPIOBRST at 0 range 1 .. 1;
GPIOCRST at 0 range 2 .. 2;
GPIODRST at 0 range 3 .. 3;
GPIOERST at 0 range 4 .. 4;
GPIOFRST at 0 range 5 .. 5;
GPIOGRST at 0 range 6 .. 6;
GPIOHRST at 0 range 7 .. 7;
GPIOIRST at 0 range 8 .. 8;
GPIOJRST at 0 range 9 .. 9;
GPIOKRST at 0 range 10 .. 10;
Reserved_11_11 at 0 range 11 .. 11;
CRCRST at 0 range 12 .. 12;
Reserved_13_20 at 0 range 13 .. 20;
DMA1RST at 0 range 21 .. 21;
DMA2RST at 0 range 22 .. 22;
DMA2DRST at 0 range 23 .. 23;
Reserved_24_24 at 0 range 24 .. 24;
ETHMACRST at 0 range 25 .. 25;
Reserved_26_28 at 0 range 26 .. 28;
OTGHSRST at 0 range 29 .. 29;
Reserved_30_31 at 0 range 30 .. 31;
end record;
subtype AHB2RSTR_DCMIRST_Field is STM32F429x.Bit;
subtype AHB2RSTR_RNGRST_Field is STM32F429x.Bit;
subtype AHB2RSTR_OTGFSRST_Field is STM32F429x.Bit;
-- AHB2 peripheral reset register
type AHB2RSTR_Register is record
-- Camera interface reset
DCMIRST : AHB2RSTR_DCMIRST_Field := 16#0#;
-- unspecified
Reserved_1_5 : STM32F429x.UInt5 := 16#0#;
-- Random number generator module reset
RNGRST : AHB2RSTR_RNGRST_Field := 16#0#;
-- USB OTG FS module reset
OTGFSRST : AHB2RSTR_OTGFSRST_Field := 16#0#;
-- unspecified
Reserved_8_31 : STM32F429x.UInt24 := 16#0#;
end record
with Object_Size => 32, Bit_Order => System.Low_Order_First;
for AHB2RSTR_Register use record
DCMIRST at 0 range 0 .. 0;
Reserved_1_5 at 0 range 1 .. 5;
RNGRST at 0 range 6 .. 6;
OTGFSRST at 0 range 7 .. 7;
Reserved_8_31 at 0 range 8 .. 31;
end record;
subtype AHB3RSTR_FMCRST_Field is STM32F429x.Bit;
-- AHB3 peripheral reset register
type AHB3RSTR_Register is record
-- Flexible memory controller module reset
FMCRST : AHB3RSTR_FMCRST_Field := 16#0#;
-- unspecified
Reserved_1_31 : STM32F429x.UInt31 := 16#0#;
end record
with Object_Size => 32, Bit_Order => System.Low_Order_First;
for AHB3RSTR_Register use record
FMCRST at 0 range 0 .. 0;
Reserved_1_31 at 0 range 1 .. 31;
end record;
subtype APB1RSTR_TIM2RST_Field is STM32F429x.Bit;
subtype APB1RSTR_TIM3RST_Field is STM32F429x.Bit;
subtype APB1RSTR_TIM4RST_Field is STM32F429x.Bit;
subtype APB1RSTR_TIM5RST_Field is STM32F429x.Bit;
subtype APB1RSTR_TIM6RST_Field is STM32F429x.Bit;
subtype APB1RSTR_TIM7RST_Field is STM32F429x.Bit;
subtype APB1RSTR_TIM12RST_Field is STM32F429x.Bit;
subtype APB1RSTR_TIM13RST_Field is STM32F429x.Bit;
subtype APB1RSTR_TIM14RST_Field is STM32F429x.Bit;
subtype APB1RSTR_WWDGRST_Field is STM32F429x.Bit;
subtype APB1RSTR_SPI2RST_Field is STM32F429x.Bit;
subtype APB1RSTR_SPI3RST_Field is STM32F429x.Bit;
subtype APB1RSTR_UART2RST_Field is STM32F429x.Bit;
subtype APB1RSTR_UART3RST_Field is STM32F429x.Bit;
subtype APB1RSTR_UART4RST_Field is STM32F429x.Bit;
subtype APB1RSTR_UART5RST_Field is STM32F429x.Bit;
subtype APB1RSTR_I2C1RST_Field is STM32F429x.Bit;
subtype APB1RSTR_I2C2RST_Field is STM32F429x.Bit;
subtype APB1RSTR_I2C3RST_Field is STM32F429x.Bit;
subtype APB1RSTR_CAN1RST_Field is STM32F429x.Bit;
subtype APB1RSTR_CAN2RST_Field is STM32F429x.Bit;
subtype APB1RSTR_PWRRST_Field is STM32F429x.Bit;
subtype APB1RSTR_DACRST_Field is STM32F429x.Bit;
subtype APB1RSTR_UART7RST_Field is STM32F429x.Bit;
subtype APB1RSTR_UART8RST_Field is STM32F429x.Bit;
-- APB1 peripheral reset register
type APB1RSTR_Register is record
-- TIM2 reset
TIM2RST : APB1RSTR_TIM2RST_Field := 16#0#;
-- TIM3 reset
TIM3RST : APB1RSTR_TIM3RST_Field := 16#0#;
-- TIM4 reset
TIM4RST : APB1RSTR_TIM4RST_Field := 16#0#;
-- TIM5 reset
TIM5RST : APB1RSTR_TIM5RST_Field := 16#0#;
-- TIM6 reset
TIM6RST : APB1RSTR_TIM6RST_Field := 16#0#;
-- TIM7 reset
TIM7RST : APB1RSTR_TIM7RST_Field := 16#0#;
-- TIM12 reset
TIM12RST : APB1RSTR_TIM12RST_Field := 16#0#;
-- TIM13 reset
TIM13RST : APB1RSTR_TIM13RST_Field := 16#0#;
-- TIM14 reset
TIM14RST : APB1RSTR_TIM14RST_Field := 16#0#;
-- unspecified
Reserved_9_10 : STM32F429x.UInt2 := 16#0#;
-- Window watchdog reset
WWDGRST : APB1RSTR_WWDGRST_Field := 16#0#;
-- unspecified
Reserved_12_13 : STM32F429x.UInt2 := 16#0#;
-- SPI 2 reset
SPI2RST : APB1RSTR_SPI2RST_Field := 16#0#;
-- SPI 3 reset
SPI3RST : APB1RSTR_SPI3RST_Field := 16#0#;
-- unspecified
Reserved_16_16 : STM32F429x.Bit := 16#0#;
-- USART 2 reset
UART2RST : APB1RSTR_UART2RST_Field := 16#0#;
-- USART 3 reset
UART3RST : APB1RSTR_UART3RST_Field := 16#0#;
-- USART 4 reset
UART4RST : APB1RSTR_UART4RST_Field := 16#0#;
-- USART 5 reset
UART5RST : APB1RSTR_UART5RST_Field := 16#0#;
-- I2C 1 reset
I2C1RST : APB1RSTR_I2C1RST_Field := 16#0#;
-- I2C 2 reset
I2C2RST : APB1RSTR_I2C2RST_Field := 16#0#;
-- I2C3 reset
I2C3RST : APB1RSTR_I2C3RST_Field := 16#0#;
-- unspecified
Reserved_24_24 : STM32F429x.Bit := 16#0#;
-- CAN1 reset
CAN1RST : APB1RSTR_CAN1RST_Field := 16#0#;
-- CAN2 reset
CAN2RST : APB1RSTR_CAN2RST_Field := 16#0#;
-- unspecified
Reserved_27_27 : STM32F429x.Bit := 16#0#;
-- Power interface reset
PWRRST : APB1RSTR_PWRRST_Field := 16#0#;
-- DAC reset
DACRST : APB1RSTR_DACRST_Field := 16#0#;
-- UART7 reset
UART7RST : APB1RSTR_UART7RST_Field := 16#0#;
-- UART8 reset
UART8RST : APB1RSTR_UART8RST_Field := 16#0#;
end record
with Object_Size => 32, Bit_Order => System.Low_Order_First;
for APB1RSTR_Register use record
TIM2RST at 0 range 0 .. 0;
TIM3RST at 0 range 1 .. 1;
TIM4RST at 0 range 2 .. 2;
TIM5RST at 0 range 3 .. 3;
TIM6RST at 0 range 4 .. 4;
TIM7RST at 0 range 5 .. 5;
TIM12RST at 0 range 6 .. 6;
TIM13RST at 0 range 7 .. 7;
TIM14RST at 0 range 8 .. 8;
Reserved_9_10 at 0 range 9 .. 10;
WWDGRST at 0 range 11 .. 11;
Reserved_12_13 at 0 range 12 .. 13;
SPI2RST at 0 range 14 .. 14;
SPI3RST at 0 range 15 .. 15;
Reserved_16_16 at 0 range 16 .. 16;
UART2RST at 0 range 17 .. 17;
UART3RST at 0 range 18 .. 18;
UART4RST at 0 range 19 .. 19;
UART5RST at 0 range 20 .. 20;
I2C1RST at 0 range 21 .. 21;
I2C2RST at 0 range 22 .. 22;
I2C3RST at 0 range 23 .. 23;
Reserved_24_24 at 0 range 24 .. 24;
CAN1RST at 0 range 25 .. 25;
CAN2RST at 0 range 26 .. 26;
Reserved_27_27 at 0 range 27 .. 27;
PWRRST at 0 range 28 .. 28;
DACRST at 0 range 29 .. 29;
UART7RST at 0 range 30 .. 30;
UART8RST at 0 range 31 .. 31;
end record;
subtype APB2RSTR_TIM1RST_Field is STM32F429x.Bit;
subtype APB2RSTR_TIM8RST_Field is STM32F429x.Bit;
subtype APB2RSTR_USART1RST_Field is STM32F429x.Bit;
subtype APB2RSTR_USART6RST_Field is STM32F429x.Bit;
subtype APB2RSTR_ADCRST_Field is STM32F429x.Bit;
subtype APB2RSTR_SDIORST_Field is STM32F429x.Bit;
subtype APB2RSTR_SPI1RST_Field is STM32F429x.Bit;
subtype APB2RSTR_SPI4RST_Field is STM32F429x.Bit;
subtype APB2RSTR_SYSCFGRST_Field is STM32F429x.Bit;
subtype APB2RSTR_TIM9RST_Field is STM32F429x.Bit;
subtype APB2RSTR_TIM10RST_Field is STM32F429x.Bit;
subtype APB2RSTR_TIM11RST_Field is STM32F429x.Bit;
subtype APB2RSTR_SPI5RST_Field is STM32F429x.Bit;
subtype APB2RSTR_SPI6RST_Field is STM32F429x.Bit;
subtype APB2RSTR_SAI1RST_Field is STM32F429x.Bit;
subtype APB2RSTR_LTDCRST_Field is STM32F429x.Bit;
-- APB2 peripheral reset register
type APB2RSTR_Register is record
-- TIM1 reset
TIM1RST : APB2RSTR_TIM1RST_Field := 16#0#;
-- TIM8 reset
TIM8RST : APB2RSTR_TIM8RST_Field := 16#0#;
-- unspecified
Reserved_2_3 : STM32F429x.UInt2 := 16#0#;
-- USART1 reset
USART1RST : APB2RSTR_USART1RST_Field := 16#0#;
-- USART6 reset
USART6RST : APB2RSTR_USART6RST_Field := 16#0#;
-- unspecified
Reserved_6_7 : STM32F429x.UInt2 := 16#0#;
-- ADC interface reset (common to all ADCs)
ADCRST : APB2RSTR_ADCRST_Field := 16#0#;
-- unspecified
Reserved_9_10 : STM32F429x.UInt2 := 16#0#;
-- SDIO reset
SDIORST : APB2RSTR_SDIORST_Field := 16#0#;
-- SPI 1 reset
SPI1RST : APB2RSTR_SPI1RST_Field := 16#0#;
-- SPI4 reset
SPI4RST : APB2RSTR_SPI4RST_Field := 16#0#;
-- System configuration controller reset
SYSCFGRST : APB2RSTR_SYSCFGRST_Field := 16#0#;
-- unspecified
Reserved_15_15 : STM32F429x.Bit := 16#0#;
-- TIM9 reset
TIM9RST : APB2RSTR_TIM9RST_Field := 16#0#;
-- TIM10 reset
TIM10RST : APB2RSTR_TIM10RST_Field := 16#0#;
-- TIM11 reset
TIM11RST : APB2RSTR_TIM11RST_Field := 16#0#;
-- unspecified
Reserved_19_19 : STM32F429x.Bit := 16#0#;
-- SPI5 reset
SPI5RST : APB2RSTR_SPI5RST_Field := 16#0#;
-- SPI6 reset
SPI6RST : APB2RSTR_SPI6RST_Field := 16#0#;
-- SAI1 reset
SAI1RST : APB2RSTR_SAI1RST_Field := 16#0#;
-- unspecified
Reserved_23_25 : STM32F429x.UInt3 := 16#0#;
-- LTDC reset
LTDCRST : APB2RSTR_LTDCRST_Field := 16#0#;
-- unspecified
Reserved_27_31 : STM32F429x.UInt5 := 16#0#;
end record
with Object_Size => 32, Bit_Order => System.Low_Order_First;
for APB2RSTR_Register use record
TIM1RST at 0 range 0 .. 0;
TIM8RST at 0 range 1 .. 1;
Reserved_2_3 at 0 range 2 .. 3;
USART1RST at 0 range 4 .. 4;
USART6RST at 0 range 5 .. 5;
Reserved_6_7 at 0 range 6 .. 7;
ADCRST at 0 range 8 .. 8;
Reserved_9_10 at 0 range 9 .. 10;
SDIORST at 0 range 11 .. 11;
SPI1RST at 0 range 12 .. 12;
SPI4RST at 0 range 13 .. 13;
SYSCFGRST at 0 range 14 .. 14;
Reserved_15_15 at 0 range 15 .. 15;
TIM9RST at 0 range 16 .. 16;
TIM10RST at 0 range 17 .. 17;
TIM11RST at 0 range 18 .. 18;
Reserved_19_19 at 0 range 19 .. 19;
SPI5RST at 0 range 20 .. 20;
SPI6RST at 0 range 21 .. 21;
SAI1RST at 0 range 22 .. 22;
Reserved_23_25 at 0 range 23 .. 25;
LTDCRST at 0 range 26 .. 26;
Reserved_27_31 at 0 range 27 .. 31;
end record;
subtype AHB1ENR_GPIOAEN_Field is STM32F429x.Bit;
subtype AHB1ENR_GPIOBEN_Field is STM32F429x.Bit;
subtype AHB1ENR_GPIOCEN_Field is STM32F429x.Bit;
subtype AHB1ENR_GPIODEN_Field is STM32F429x.Bit;
subtype AHB1ENR_GPIOEEN_Field is STM32F429x.Bit;
subtype AHB1ENR_GPIOFEN_Field is STM32F429x.Bit;
subtype AHB1ENR_GPIOGEN_Field is STM32F429x.Bit;
subtype AHB1ENR_GPIOHEN_Field is STM32F429x.Bit;
subtype AHB1ENR_GPIOIEN_Field is STM32F429x.Bit;
subtype AHB1ENR_GPIOJEN_Field is STM32F429x.Bit;
subtype AHB1ENR_GPIOKEN_Field is STM32F429x.Bit;
subtype AHB1ENR_CRCEN_Field is STM32F429x.Bit;
subtype AHB1ENR_BKPSRAMEN_Field is STM32F429x.Bit;
subtype AHB1ENR_CCMDATARAMEN_Field is STM32F429x.Bit;
subtype AHB1ENR_DMA1EN_Field is STM32F429x.Bit;
subtype AHB1ENR_DMA2EN_Field is STM32F429x.Bit;
subtype AHB1ENR_DMA2DEN_Field is STM32F429x.Bit;
subtype AHB1ENR_ETHMACEN_Field is STM32F429x.Bit;
subtype AHB1ENR_ETHMACTXEN_Field is STM32F429x.Bit;
subtype AHB1ENR_ETHMACRXEN_Field is STM32F429x.Bit;
subtype AHB1ENR_ETHMACPTPEN_Field is STM32F429x.Bit;
subtype AHB1ENR_OTGHSEN_Field is STM32F429x.Bit;
subtype AHB1ENR_OTGHSULPIEN_Field is STM32F429x.Bit;
-- AHB1 peripheral clock register
type AHB1ENR_Register is record
-- IO port A clock enable
GPIOAEN : AHB1ENR_GPIOAEN_Field := 16#0#;
-- IO port B clock enable
GPIOBEN : AHB1ENR_GPIOBEN_Field := 16#0#;
-- IO port C clock enable
GPIOCEN : AHB1ENR_GPIOCEN_Field := 16#0#;
-- IO port D clock enable
GPIODEN : AHB1ENR_GPIODEN_Field := 16#0#;
-- IO port E clock enable
GPIOEEN : AHB1ENR_GPIOEEN_Field := 16#0#;
-- IO port F clock enable
GPIOFEN : AHB1ENR_GPIOFEN_Field := 16#0#;
-- IO port G clock enable
GPIOGEN : AHB1ENR_GPIOGEN_Field := 16#0#;
-- IO port H clock enable
GPIOHEN : AHB1ENR_GPIOHEN_Field := 16#0#;
-- IO port I clock enable
GPIOIEN : AHB1ENR_GPIOIEN_Field := 16#0#;
-- IO port J clock enable
GPIOJEN : AHB1ENR_GPIOJEN_Field := 16#0#;
-- IO port K clock enable
GPIOKEN : AHB1ENR_GPIOKEN_Field := 16#0#;
-- unspecified
Reserved_11_11 : STM32F429x.Bit := 16#0#;
-- CRC clock enable
CRCEN : AHB1ENR_CRCEN_Field := 16#0#;
-- unspecified
Reserved_13_17 : STM32F429x.UInt5 := 16#0#;
-- Backup SRAM interface clock enable
BKPSRAMEN : AHB1ENR_BKPSRAMEN_Field := 16#0#;
-- unspecified
Reserved_19_19 : STM32F429x.Bit := 16#0#;
-- CCM data RAM clock enable
CCMDATARAMEN : AHB1ENR_CCMDATARAMEN_Field := 16#1#;
-- DMA1 clock enable
DMA1EN : AHB1ENR_DMA1EN_Field := 16#0#;
-- DMA2 clock enable
DMA2EN : AHB1ENR_DMA2EN_Field := 16#0#;
-- DMA2D clock enable
DMA2DEN : AHB1ENR_DMA2DEN_Field := 16#0#;
-- unspecified
Reserved_24_24 : STM32F429x.Bit := 16#0#;
-- Ethernet MAC clock enable
ETHMACEN : AHB1ENR_ETHMACEN_Field := 16#0#;
-- Ethernet Transmission clock enable
ETHMACTXEN : AHB1ENR_ETHMACTXEN_Field := 16#0#;
-- Ethernet Reception clock enable
ETHMACRXEN : AHB1ENR_ETHMACRXEN_Field := 16#0#;
-- Ethernet PTP clock enable
ETHMACPTPEN : AHB1ENR_ETHMACPTPEN_Field := 16#0#;
-- USB OTG HS clock enable
OTGHSEN : AHB1ENR_OTGHSEN_Field := 16#0#;
-- USB OTG HSULPI clock enable
OTGHSULPIEN : AHB1ENR_OTGHSULPIEN_Field := 16#0#;
-- unspecified
Reserved_31_31 : STM32F429x.Bit := 16#0#;
end record
with Object_Size => 32, Bit_Order => System.Low_Order_First;
for AHB1ENR_Register use record
GPIOAEN at 0 range 0 .. 0;
GPIOBEN at 0 range 1 .. 1;
GPIOCEN at 0 range 2 .. 2;
GPIODEN at 0 range 3 .. 3;
GPIOEEN at 0 range 4 .. 4;
GPIOFEN at 0 range 5 .. 5;
GPIOGEN at 0 range 6 .. 6;
GPIOHEN at 0 range 7 .. 7;
GPIOIEN at 0 range 8 .. 8;
GPIOJEN at 0 range 9 .. 9;
GPIOKEN at 0 range 10 .. 10;
Reserved_11_11 at 0 range 11 .. 11;
CRCEN at 0 range 12 .. 12;
Reserved_13_17 at 0 range 13 .. 17;
BKPSRAMEN at 0 range 18 .. 18;
Reserved_19_19 at 0 range 19 .. 19;
CCMDATARAMEN at 0 range 20 .. 20;
DMA1EN at 0 range 21 .. 21;
DMA2EN at 0 range 22 .. 22;
DMA2DEN at 0 range 23 .. 23;
Reserved_24_24 at 0 range 24 .. 24;
ETHMACEN at 0 range 25 .. 25;
ETHMACTXEN at 0 range 26 .. 26;
ETHMACRXEN at 0 range 27 .. 27;
ETHMACPTPEN at 0 range 28 .. 28;
OTGHSEN at 0 range 29 .. 29;
OTGHSULPIEN at 0 range 30 .. 30;
Reserved_31_31 at 0 range 31 .. 31;
end record;
subtype AHB2ENR_DCMIEN_Field is STM32F429x.Bit;
subtype AHB2ENR_RNGEN_Field is STM32F429x.Bit;
subtype AHB2ENR_OTGFSEN_Field is STM32F429x.Bit;
-- AHB2 peripheral clock enable register
type AHB2ENR_Register is record
-- Camera interface enable
DCMIEN : AHB2ENR_DCMIEN_Field := 16#0#;
-- unspecified
Reserved_1_5 : STM32F429x.UInt5 := 16#0#;
-- Random number generator clock enable
RNGEN : AHB2ENR_RNGEN_Field := 16#0#;
-- USB OTG FS clock enable
OTGFSEN : AHB2ENR_OTGFSEN_Field := 16#0#;
-- unspecified
Reserved_8_31 : STM32F429x.UInt24 := 16#0#;
end record
with Object_Size => 32, Bit_Order => System.Low_Order_First;
for AHB2ENR_Register use record
DCMIEN at 0 range 0 .. 0;
Reserved_1_5 at 0 range 1 .. 5;
RNGEN at 0 range 6 .. 6;
OTGFSEN at 0 range 7 .. 7;
Reserved_8_31 at 0 range 8 .. 31;
end record;
subtype AHB3ENR_FMCEN_Field is STM32F429x.Bit;
-- AHB3 peripheral clock enable register
type AHB3ENR_Register is record
-- Flexible memory controller module clock enable
FMCEN : AHB3ENR_FMCEN_Field := 16#0#;
-- unspecified
Reserved_1_31 : STM32F429x.UInt31 := 16#0#;
end record
with Object_Size => 32, Bit_Order => System.Low_Order_First;
for AHB3ENR_Register use record
FMCEN at 0 range 0 .. 0;
Reserved_1_31 at 0 range 1 .. 31;
end record;
subtype APB1ENR_TIM2EN_Field is STM32F429x.Bit;
subtype APB1ENR_TIM3EN_Field is STM32F429x.Bit;
subtype APB1ENR_TIM4EN_Field is STM32F429x.Bit;
subtype APB1ENR_TIM5EN_Field is STM32F429x.Bit;
subtype APB1ENR_TIM6EN_Field is STM32F429x.Bit;
subtype APB1ENR_TIM7EN_Field is STM32F429x.Bit;
subtype APB1ENR_TIM12EN_Field is STM32F429x.Bit;
subtype APB1ENR_TIM13EN_Field is STM32F429x.Bit;
subtype APB1ENR_TIM14EN_Field is STM32F429x.Bit;
subtype APB1ENR_WWDGEN_Field is STM32F429x.Bit;
subtype APB1ENR_SPI2EN_Field is STM32F429x.Bit;
subtype APB1ENR_SPI3EN_Field is STM32F429x.Bit;
subtype APB1ENR_USART2EN_Field is STM32F429x.Bit;
subtype APB1ENR_USART3EN_Field is STM32F429x.Bit;
subtype APB1ENR_UART4EN_Field is STM32F429x.Bit;
subtype APB1ENR_UART5EN_Field is STM32F429x.Bit;
subtype APB1ENR_I2C1EN_Field is STM32F429x.Bit;
subtype APB1ENR_I2C2EN_Field is STM32F429x.Bit;
subtype APB1ENR_I2C3EN_Field is STM32F429x.Bit;
subtype APB1ENR_CAN1EN_Field is STM32F429x.Bit;
subtype APB1ENR_CAN2EN_Field is STM32F429x.Bit;
subtype APB1ENR_PWREN_Field is STM32F429x.Bit;
subtype APB1ENR_DACEN_Field is STM32F429x.Bit;
subtype APB1ENR_UART7ENR_Field is STM32F429x.Bit;
subtype APB1ENR_UART8ENR_Field is STM32F429x.Bit;
-- APB1 peripheral clock enable register
type APB1ENR_Register is record
-- TIM2 clock enable
TIM2EN : APB1ENR_TIM2EN_Field := 16#0#;
-- TIM3 clock enable
TIM3EN : APB1ENR_TIM3EN_Field := 16#0#;
-- TIM4 clock enable
TIM4EN : APB1ENR_TIM4EN_Field := 16#0#;
-- TIM5 clock enable
TIM5EN : APB1ENR_TIM5EN_Field := 16#0#;
-- TIM6 clock enable
TIM6EN : APB1ENR_TIM6EN_Field := 16#0#;
-- TIM7 clock enable
TIM7EN : APB1ENR_TIM7EN_Field := 16#0#;
-- TIM12 clock enable
TIM12EN : APB1ENR_TIM12EN_Field := 16#0#;
-- TIM13 clock enable
TIM13EN : APB1ENR_TIM13EN_Field := 16#0#;
-- TIM14 clock enable
TIM14EN : APB1ENR_TIM14EN_Field := 16#0#;
-- unspecified
Reserved_9_10 : STM32F429x.UInt2 := 16#0#;
-- Window watchdog clock enable
WWDGEN : APB1ENR_WWDGEN_Field := 16#0#;
-- unspecified
Reserved_12_13 : STM32F429x.UInt2 := 16#0#;
-- SPI2 clock enable
SPI2EN : APB1ENR_SPI2EN_Field := 16#0#;
-- SPI3 clock enable
SPI3EN : APB1ENR_SPI3EN_Field := 16#0#;
-- unspecified
Reserved_16_16 : STM32F429x.Bit := 16#0#;
-- USART 2 clock enable
USART2EN : APB1ENR_USART2EN_Field := 16#0#;
-- USART3 clock enable
USART3EN : APB1ENR_USART3EN_Field := 16#0#;
-- UART4 clock enable
UART4EN : APB1ENR_UART4EN_Field := 16#0#;
-- UART5 clock enable
UART5EN : APB1ENR_UART5EN_Field := 16#0#;
-- I2C1 clock enable
I2C1EN : APB1ENR_I2C1EN_Field := 16#0#;
-- I2C2 clock enable
I2C2EN : APB1ENR_I2C2EN_Field := 16#0#;
-- I2C3 clock enable
I2C3EN : APB1ENR_I2C3EN_Field := 16#0#;
-- unspecified
Reserved_24_24 : STM32F429x.Bit := 16#0#;
-- CAN 1 clock enable
CAN1EN : APB1ENR_CAN1EN_Field := 16#0#;
-- CAN 2 clock enable
CAN2EN : APB1ENR_CAN2EN_Field := 16#0#;
-- unspecified
Reserved_27_27 : STM32F429x.Bit := 16#0#;
-- Power interface clock enable
PWREN : APB1ENR_PWREN_Field := 16#0#;
-- DAC interface clock enable
DACEN : APB1ENR_DACEN_Field := 16#0#;
-- UART7 clock enable
UART7ENR : APB1ENR_UART7ENR_Field := 16#0#;
-- UART8 clock enable
UART8ENR : APB1ENR_UART8ENR_Field := 16#0#;
end record
with Object_Size => 32, Bit_Order => System.Low_Order_First;
for APB1ENR_Register use record
TIM2EN at 0 range 0 .. 0;
TIM3EN at 0 range 1 .. 1;
TIM4EN at 0 range 2 .. 2;
TIM5EN at 0 range 3 .. 3;
TIM6EN at 0 range 4 .. 4;
TIM7EN at 0 range 5 .. 5;
TIM12EN at 0 range 6 .. 6;
TIM13EN at 0 range 7 .. 7;
TIM14EN at 0 range 8 .. 8;
Reserved_9_10 at 0 range 9 .. 10;
WWDGEN at 0 range 11 .. 11;
Reserved_12_13 at 0 range 12 .. 13;
SPI2EN at 0 range 14 .. 14;
SPI3EN at 0 range 15 .. 15;
Reserved_16_16 at 0 range 16 .. 16;
USART2EN at 0 range 17 .. 17;
USART3EN at 0 range 18 .. 18;
UART4EN at 0 range 19 .. 19;
UART5EN at 0 range 20 .. 20;
I2C1EN at 0 range 21 .. 21;
I2C2EN at 0 range 22 .. 22;
I2C3EN at 0 range 23 .. 23;
Reserved_24_24 at 0 range 24 .. 24;
CAN1EN at 0 range 25 .. 25;
CAN2EN at 0 range 26 .. 26;
Reserved_27_27 at 0 range 27 .. 27;
PWREN at 0 range 28 .. 28;
DACEN at 0 range 29 .. 29;
UART7ENR at 0 range 30 .. 30;
UART8ENR at 0 range 31 .. 31;
end record;
subtype APB2ENR_TIM1EN_Field is STM32F429x.Bit;
subtype APB2ENR_TIM8EN_Field is STM32F429x.Bit;
subtype APB2ENR_USART1EN_Field is STM32F429x.Bit;
subtype APB2ENR_USART6EN_Field is STM32F429x.Bit;
subtype APB2ENR_ADC1EN_Field is STM32F429x.Bit;
subtype APB2ENR_ADC2EN_Field is STM32F429x.Bit;
subtype APB2ENR_ADC3EN_Field is STM32F429x.Bit;
subtype APB2ENR_SDIOEN_Field is STM32F429x.Bit;
subtype APB2ENR_SPI1EN_Field is STM32F429x.Bit;
subtype APB2ENR_SPI4ENR_Field is STM32F429x.Bit;
subtype APB2ENR_SYSCFGEN_Field is STM32F429x.Bit;
subtype APB2ENR_TIM9EN_Field is STM32F429x.Bit;
subtype APB2ENR_TIM10EN_Field is STM32F429x.Bit;
subtype APB2ENR_TIM11EN_Field is STM32F429x.Bit;
subtype APB2ENR_SPI5ENR_Field is STM32F429x.Bit;
subtype APB2ENR_SPI6ENR_Field is STM32F429x.Bit;
subtype APB2ENR_SAI1EN_Field is STM32F429x.Bit;
subtype APB2ENR_LTDCEN_Field is STM32F429x.Bit;
-- APB2 peripheral clock enable register
type APB2ENR_Register is record
-- TIM1 clock enable
TIM1EN : APB2ENR_TIM1EN_Field := 16#0#;
-- TIM8 clock enable
TIM8EN : APB2ENR_TIM8EN_Field := 16#0#;
-- unspecified
Reserved_2_3 : STM32F429x.UInt2 := 16#0#;
-- USART1 clock enable
USART1EN : APB2ENR_USART1EN_Field := 16#0#;
-- USART6 clock enable
USART6EN : APB2ENR_USART6EN_Field := 16#0#;
-- unspecified
Reserved_6_7 : STM32F429x.UInt2 := 16#0#;
-- ADC1 clock enable
ADC1EN : APB2ENR_ADC1EN_Field := 16#0#;
-- ADC2 clock enable
ADC2EN : APB2ENR_ADC2EN_Field := 16#0#;
-- ADC3 clock enable
ADC3EN : APB2ENR_ADC3EN_Field := 16#0#;
-- SDIO clock enable
SDIOEN : APB2ENR_SDIOEN_Field := 16#0#;
-- SPI1 clock enable
SPI1EN : APB2ENR_SPI1EN_Field := 16#0#;
-- SPI4 clock enable
SPI4ENR : APB2ENR_SPI4ENR_Field := 16#0#;
-- System configuration controller clock enable
SYSCFGEN : APB2ENR_SYSCFGEN_Field := 16#0#;
-- unspecified
Reserved_15_15 : STM32F429x.Bit := 16#0#;
-- TIM9 clock enable
TIM9EN : APB2ENR_TIM9EN_Field := 16#0#;
-- TIM10 clock enable
TIM10EN : APB2ENR_TIM10EN_Field := 16#0#;
-- TIM11 clock enable
TIM11EN : APB2ENR_TIM11EN_Field := 16#0#;