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Fixes Linux commands and SystemC simulation of counter #11

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Fixes Linux commands and SystemC simulation of counter #11

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ShashankVM
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To fix Issue #9

  1. Fixes Linux commands in the doc (tex file).
  2. Enhanced testbench for counter simulation so it won't hang. Counter simulation now looks like this:

        SystemC 2.3.3-Accellera --- Jun 16 2021 21:27:55
        Copyright (c) 1996-2018 by all Contributors,
        ALL RIGHTS RESERVED
Clock           Time            Reset           Counter         Even
0               0 s             0               0               0
1               1 ns            1               1               0
1               2 ns            0               0               1
1               5 ns            1               1               0
1               6 ns            1               2               1
1               7 ns            1               3               0
1               8 ns            1               4               1
1               9 ns            1               5               0
1               10 ns           1               6               1
1               11 ns           1               7               0
1               12 ns           1               8               1
1               13 ns           1               9               0
1               14 ns           1               10              1
1               15 ns           1               11              0
1               16 ns           1               12              1
1               17 ns           1               13              0
1               18 ns           1               14              1
1               19 ns           1               15              0
1               20 ns           1               0               1
1               21 ns           1               1               0

                *****Simulation complete*****

On second command, it is not required to do "mkdir build" since build directory already exists. The counter example folder is in "build/icsc/examples", not "build/examples".
Simulation used to hang since the time to stop was not mentioned. I fixed this. I also added a function to test reset and to print the signals and to print a message "simulation complete" once the simulation is done. This gives the user a feedback of the simulation results.

The output now looks like this:

```
shashank@shashank-desktop:~/systemc-compiler/build$ cd icsc/examples/counter && ./counter

        SystemC 2.3.3-Accellera --- Jun 16 2021 21:27:55
        Copyright (c) 1996-2018 by all Contributors,
        ALL RIGHTS RESERVED
Clock           Time            Reset           Counter         Even
0               0 s             0               0               0
1               1 ns            1               1               0
1               2 ns            0               0               1
1               5 ns            1               1               0
1               6 ns            1               2               1
1               7 ns            1               3               0
1               8 ns            1               4               1
1               9 ns            1               5               0
1               10 ns           1               6               1
1               11 ns           1               7               0
1               12 ns           1               8               1
1               13 ns           1               9               0
1               14 ns           1               10              1
1               15 ns           1               11              0
1               16 ns           1               12              1
1               17 ns           1               13              0
1               18 ns           1               14              1
1               19 ns           1               15              0
1               20 ns           1               0               1
1               21 ns           1               1               0

                *****Simulation complete*****
shashank@shashank-desktop:~/systemc-compiler/build/icsc/examples/counter$  

```
Enhanced testbench and stopped simulation hanging
Fixed guide section "Run SystemC simulation"
Fixed Linux commands for running SystemC simulation and viewing SV file.
@mikhailmoiseev
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Hi @ShashankVM. Have accepted your pull request. It will be available in the next update of the repo, suppose next week.

@ShashankVM
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ShashankVM commented Jun 19, 2021

@mikhailmoiseev thanks. I'd like it if you merge my pull request on GitHub in the next version. I am also planning to contribute more, especially to the SystemC temporal assertions library. Currently the assertions library does not support reuse of properties like those in SystemVerilog. Also the syntax of SystemC Temporal Assertions is not as concise as SVA.

@mikhailmoiseev
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This repo is a copy of an internal one, so no direct merge is possible. All issues found and bug fixes are welcome. The SystemC assertions are under discussion in SystemC LWG, so its functionality is frozen for now.

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2 participants