Signals stuck at X

[pmerz1]

Hi,

I am currently testing this compiler and I had a problem simulating the generated SV modules with different tools.

I have implemented a producer and a consumer module that communicate via a channel.
In the sockets for the channel on the consumer and producer side, I have implemented a simple CDC module that performs pipelining of an input signal.

This CDC module behaves differently in several simulators.

In SystemC, I've written following:

template <class T>
SC_MODULE(CDC)
{
    sc_in < T > SC_NAMED(sig_in_p); 
    sc_in < bool > SC_NAMED(rstn); 
    sc_in < bool > SC_NAMED(new_clk_dom_p); 
    sc_out < T > SC_NAMED(sig_out_p) ; 
    uint m_size ; //!< size of internal pipeline */
    sc_vector < sc_signal < T > > SC_NAMED(buffer_reg_s) ; //!< vector for buffering */

    CDC ( sc_module_name _nm, uint size) 
    : sc_module {_nm}, m_size {MIN_CDC_SIZE+size}
    {
        buffer_reg_s.init(m_size);
        SC_HAS_PROCESS(CDC);
        SC_THREAD(mthd_buffering);
        sensitive << new_clk_dom_p.pos();
        async_reset_signal_is(rstn, 0);

    };

    void mthd_buffering()
    {
        buffer_reg_s[0].write(0);
        for (uint i = 0; i < m_size-1;i++)
        {
            buffer_reg_s[i+1].write(0);
        }
        sig_out_p.write(0); 
        wait();
        while(1)
        {
            buffer_reg_s[0].write(sig_in_p.read());
            for (uint i = 0; i < m_size-1;i++)
            {
                buffer_reg_s[i+1].write(buffer_reg_s[i].read());
            }
            sig_out_p.write(buffer_reg_s[m_size-1].read()); 
            wait();
        }
    };
};

The generated SV module looks like:

//==============================================================================
//
// Module: CDC (chan_Producer.h:168:5)
//
module CDC // "tb.dut.prod_0.init_fsm.cdc_core_ready"
(
    input logic sig_in_p,
    input logic rstn,
    input logic new_clk_dom_p,
    output logic sig_out_p
);

// Variables generated for SystemC signals
logic buffer_reg_s[2];

// Local parameters generated for C++ constants
localparam logic [31:0] m_size = 2;

//------------------------------------------------------------------------------
// Clocked THREAD: mthd_buffering (sc_cdc.h:138:5) 

// Thread-local variables
logic buffer_reg_s_next[2];
logic sig_out_p_next;

// Next-state combinational logic
always_comb begin : mthd_buffering_comb     // sc_cdc.h:138:5
    mthd_buffering_func;
end
function void mthd_buffering_func;
    buffer_reg_s_next = buffer_reg_s;
    sig_out_p_next = sig_out_p;
    buffer_reg_s_next[0] = sig_in_p;
    for (integer unsigned i_1 = 0; i_1 < m_size - 1; i_1++)
    begin
        buffer_reg_s_next[i_1 + 1] = buffer_reg_s[i_1];
    end
    sig_out_p_next = buffer_reg_s[m_size - 1];
endfunction

// Synchronous register update
always_ff @(posedge new_clk_dom_p or negedge rstn) 
begin : mthd_buffering_ff
    if ( ~rstn ) begin
        buffer_reg_s[0] <= 0;
        for (integer unsigned i = 0; i < m_size - 1; i++)
        begin
            buffer_reg_s[i + 1] <= 0;
        end
        sig_out_p <= 0;
    end
    else begin
        buffer_reg_s <= buffer_reg_s_next;
        sig_out_p <= sig_out_p_next;
    end
end

endmodule

I executed the code with three different simlulators and have following results for this simple CDC module:

Vivado2018.3 (The Divider is named Producer but I meant CDC)

Vivado2023.2

XCELIUM2209

As you can see, the CDC module works perfectly well with two of the three simulators.
When using Vivado 2018.3, several signals like sig_out_p_next and buffer_reg_s_next get stuck on X.
After releasing the negative reset in particular, sig_out_p and buffer_reg_s also get stuck on X.

I realize that you may not be familiar with these simulator tools. I am just wondering why this behavior occurs in VIVADO2018.3. I hope you have had this problem in the past.

[mikhailmoiseev]

I have never worked with Vivado. I am using commercial simulators for ASIC and of course OSCI SystemC simulator.
The issue looks like a bug in Vivado 2018. If you like to investigate it, it would make sense to ask Vivado support.
Do you see any issue with the generated SV?