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Equivalence Checking - SystemC vs. Generated SystemVerilog #12

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ShashankVM opened this issue Jul 29, 2021 · 2 comments
Closed

Equivalence Checking - SystemC vs. Generated SystemVerilog #12

ShashankVM opened this issue Jul 29, 2021 · 2 comments

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@ShashankVM
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Greetings,

This is a feature request for equivalence checking of the synthesized SystemVerilog code vs the SystemC design. Is such an enhancement planned?

Regards,
Shashank V M
@mikhailmoiseev
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It needs some volunteer for this work. If you are interested in that, can discuss the details.

@ShashankVM
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@mikhailmoiseev yes, I'll be happy to work on this project.

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@ShashankVM @mikhailmoiseev