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2 files changed +14
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lines changed Original file line number Diff line number Diff line change @@ -240,7 +240,12 @@ void initVariant( void )
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variantGpioInit ();
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variantPwmInit ();
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variantAdcInit ();
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-
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+
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+ // set RTC clock divider to 32768(1 Hz)
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+ *SYS_CLK_CTL |= RTC_DIV_1HZ_MASK;
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+ *SYS_CLK_CTL &= ~(1 << CCU_RTC_CLK_DIV_EN);
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+ *SYS_CLK_CTL |= 1 << CCU_RTC_CLK_DIV_EN;
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+
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cfw_platform_init ();
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// Add for debug corelib
Original file line number Diff line number Diff line change @@ -146,6 +146,14 @@ extern "C"{
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#define ADC_RESOLUTION 12
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#define ADC_CLOCK_GATE (1 << 31)
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+ /*
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+ * Clocking
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+ */
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+
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+ #define SYS_CLK_CTL (volatile int*)0xB0800038
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+ #define CCU_RTC_CLK_DIV_EN 2
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+ #define RTC_DIV_1HZ_MASK 0x00000078
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+
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#define digitalPinToBitMask (P ) (1 << g_APinDescription[P].ulGPIOId)
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//static uint8_t __unused_var_POR;
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