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MIPS: mscc: Add serval support
Add a device trees and FIT image support for the Microsemi Serval SoC which belongs to same family of the Ocelot SoC. It is based on the work of Lars Povlsen <lars.povlsen@microchip.com>. Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com> Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
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‎arch/mips/boot/dts/mscc/Makefile

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -5,6 +5,9 @@ dtb-$(CONFIG_SOC_VCOREIII) += \
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jaguar2_pcb118.dtb \
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luton_pcb091.dtb \
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ocelot_pcb120.dtb \
8-
ocelot_pcb123.dtb
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ocelot_pcb123.dtb \
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serval_pcb105.dtb \
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serval_pcb106.dtb
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obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y))

‎arch/mips/boot/dts/mscc/serval.dtsi

Lines changed: 153 additions & 0 deletions
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@@ -0,0 +1,153 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2018 Microsemi Corporation
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*/
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "mscc,serval";
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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compatible = "mips,mips24KEc";
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device_type = "cpu";
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clocks = <&cpu_clk>;
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reg = <0>;
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};
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};
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aliases {
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serial0 = &uart0;
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gpio0 = &gpio;
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};
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cpuintc: interrupt-controller {
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-controller;
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compatible = "mti,cpu-interrupt-controller";
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};
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cpu_clk: cpu-clock {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <416666666>;
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};
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ahb_clk: ahb-clk {
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compatible = "fixed-factor-clock";
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#clock-cells = <0>;
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clocks = <&cpu_clk>;
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clock-div = <2>;
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clock-mult = <1>;
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};
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ahb: ahb {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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interrupt-parent = <&intc>;
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cpu_ctrl: syscon@70000000 {
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compatible = "mscc,ocelot-cpu-syscon", "syscon";
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reg = <0x70000000 0x2c>;
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};
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intc: interrupt-controller@70000070 {
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compatible = "mscc,serval-icpu-intr";
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reg = <0x70000070 0x70>;
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#interrupt-cells = <1>;
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interrupt-controller;
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interrupt-parent = <&cpuintc>;
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interrupts = <2>;
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};
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uart0: serial@70100000 {
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pinctrl-0 = <&uart_pins>;
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pinctrl-names = "default";
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compatible = "ns16550a";
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reg = <0x70100000 0x20>;
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interrupts = <6>;
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clocks = <&ahb_clk>;
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reg-io-width = <4>;
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reg-shift = <2>;
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status = "disabled";
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};
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uart2: serial@70100800 {
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pinctrl-0 = <&uart2_pins>;
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pinctrl-names = "default";
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compatible = "ns16550a";
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reg = <0x70100800 0x20>;
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interrupts = <7>;
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clocks = <&ahb_clk>;
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reg-io-width = <4>;
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reg-shift = <2>;
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status = "disabled";
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};
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gpio: pinctrl@71070034 {
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compatible = "mscc,serval-pinctrl";
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reg = <0x71070034 0x28>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&gpio 0 0 22>;
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sgpio_pins: sgpio-pins {
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pins = "GPIO_0", "GPIO_2", "GPIO_3", "GPIO_1";
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function = "sg0";
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};
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i2c_pins: i2c-pins {
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pins = "GPIO_6", "GPIO_7";
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function = "twi";
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};
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uart_pins: uart-pins {
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pins = "GPIO_26", "GPIO_27";
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function = "uart";
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};
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uart2_pins: uart2-pins {
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pins = "GPIO_13", "GPIO_14";
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function = "uart2";
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};
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cs1_pins: cs1-pins {
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pins = "GPIO_8";
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function = "si";
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};
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irqext0_pins: irqext0-pins {
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pins = "GPIO_28";
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function = "irq0";
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};
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irqext1_pins: irqext1-pins {
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pins = "GPIO_29";
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function = "irq1";
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};
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};
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i2c0: i2c@70100400 {
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compatible = "mscc,ocelot-i2c", "snps,designware-i2c";
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status = "disabled";
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pinctrl-0 = <&i2c_pins>;
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pinctrl-names = "default";
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reg = <0x70100400 0x100>, <0x70000190 0x8>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <8>;
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clock-frequency = <100000>;
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clocks = <&ahb_clk>;
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};
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};
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};

‎arch/mips/boot/dts/mscc/serval_common.dtsi

Lines changed: 127 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,127 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2020 Microsemi Corporation
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*/
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#include "serval.dtsi"
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/ {
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aliases {
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serial0 = &uart0;
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i2c104 = &i2c104;
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i2c105 = &i2c105;
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i2c106 = &i2c106;
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i2c107 = &i2c107;
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i2c108 = &i2c108;
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i2c109 = &i2c109;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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i2c0_imux: i2c0-imux{
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compatible = "i2c-mux-pinctrl";
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#address-cells = <1>;
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#size-cells = <0>;
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i2c-parent = <&i2c0>;
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pinctrl-names =
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"i2c104", "i2c105", "i2c106", "i2c107",
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"i2c108", "i2c109", "idle";
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pinctrl-0 = <&i2cmux_0>;
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pinctrl-1 = <&i2cmux_1>;
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pinctrl-2 = <&i2cmux_2>;
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pinctrl-3 = <&i2cmux_3>;
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pinctrl-4 = <&i2cmux_4>;
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pinctrl-5 = <&i2cmux_5>;
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pinctrl-6 = <&i2cmux_pins_i>;
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i2c104: i2c_sfp0@0 {
39+
reg = <0>;
40+
#address-cells = <1>;
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#size-cells = <0>;
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};
43+
i2c105: i2c_sfp1@1 {
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reg = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
48+
i2c106: i2c_sfp2@2 {
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reg = <2>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
53+
i2c107: i2c_sfp3@3 {
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reg = <3>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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i2c108: i2c_sfp4@4 {
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reg = <4>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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i2c109: i2c_sfp5@5 {
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reg = <5>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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};
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};
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&uart0 {
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status = "okay";
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};
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&uart2 {
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status = "okay";
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};
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&gpio {
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i2c_pins: i2c-pins {
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pins = "GPIO_7"; /* No "default" scl for i2c0 */
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function = "twi";
84+
};
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i2cmux_pins_i: i2cmux-pins-i {
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pins = "GPIO_11", "GPIO_12", "GPIO_18", "GPIO_19",
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"GPIO_20", "GPIO_21";
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function = "twi_scl_m";
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output-low;
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};
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i2cmux_0: i2cmux-0 {
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pins = "GPIO_11";
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function = "twi_scl_m";
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output-high;
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};
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i2cmux_1: i2cmux-1 {
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pins = "GPIO_12";
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function = "twi_scl_m";
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output-high;
100+
};
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i2cmux_2: i2cmux-2 {
102+
pins = "GPIO_18";
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function = "twi_scl_m";
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output-high;
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};
106+
i2cmux_3: i2cmux-3 {
107+
pins = "GPIO_19";
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function = "twi_scl_m";
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output-high;
110+
};
111+
i2cmux_4: i2cmux-4 {
112+
pins = "GPIO_20";
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function = "twi_scl_m";
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output-high;
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};
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i2cmux_5: i2cmux-5 {
117+
pins = "GPIO_21";
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function = "twi_scl_m";
119+
output-high;
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};
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};
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&i2c0 {
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status = "okay";
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i2c-sda-hold-time-ns = <300>;
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};
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‎arch/mips/boot/dts/mscc/serval_pcb105.dts

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@@ -0,0 +1,17 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2018 Microsemi Corporation
4+
*/
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6+
/dts-v1/;
7+
#include "serval_common.dtsi"
8+
9+
/ {
10+
model = "Serval PCB105 Reference Board";
11+
compatible = "mscc,serval-pcb105", "mscc,serval";
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aliases {
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};
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};
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‎arch/mips/boot/dts/mscc/serval_pcb106.dts

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@@ -0,0 +1,17 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2018 Microsemi Corporation
4+
*/
5+
6+
/dts-v1/;
7+
#include "serval_common.dtsi"
8+
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/ {
10+
model = "Serval PCB106 Reference Board";
11+
compatible = "mscc,serval-pcb106", "mscc,serval";
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aliases {
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};
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};
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‎arch/mips/generic/Kconfig

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Original file line numberDiff line numberDiff line change
@@ -94,6 +94,14 @@ config FIT_IMAGE_FDT_JAGUAR2
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from Microsemi in the FIT kernel image.
9595
This requires u-boot on the platform.
9696

97+
config FIT_IMAGE_FDT_SERVAL
98+
bool "Include FDT for Microsemi Serval development platforms"
99+
select SOC_VCOREIII
100+
help
101+
Enable this to include the FDT for the Serval development platforms
102+
from Microsemi in the FIT kernel image.
103+
This requires u-boot on the platform.
104+
97105
config BOARD_INGENIC
98106
bool "Support boards based on Ingenic SoCs"
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select MACH_INGENIC_GENERIC

‎arch/mips/generic/Platform

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Original file line numberDiff line numberDiff line change
@@ -22,4 +22,5 @@ its-$(CONFIG_FIT_IMAGE_FDT_NI169445) += board-ni169445.its.S
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its-$(CONFIG_FIT_IMAGE_FDT_OCELOT) += board-ocelot.its.S
2323
its-$(CONFIG_FIT_IMAGE_FDT_LUTON) += board-luton.its.S
2424
its-$(CONFIG_FIT_IMAGE_FDT_JAGUAR2) += board-jaguar2.its.S
25+
its-$(CONFIG_FIT_IMAGE_FDT_SERVAL) += board-serval.its.S
2526
its-$(CONFIG_FIT_IMAGE_FDT_XILFPGA) += board-xilfpga.its.S

‎arch/mips/generic/board-serval.its.S

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/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
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/ {
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images {
4+
fdt@serval_pcb105 {
5+
description = "MSCC Serval PCB105 Device Tree";
6+
data = /incbin/("boot/dts/mscc/serval_pcb105.dtb");
7+
type = "flat_dt";
8+
arch = "mips";
9+
compression = "none";
10+
hash@0 {
11+
algo = "sha1";
12+
};
13+
};
14+
};
15+
16+
configurations {
17+
pcb105 {
18+
description = "Serval Linux kernel";
19+
kernel = "kernel@0";
20+
fdt = "fdt@serval_pcb105";
21+
ramdisk = "ramdisk";
22+
};
23+
};
24+
};

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