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Merge tag 'renesas-pinctrl-for-v6.10-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel
pinctrl: renesas: Updates for v6.10 - Add external interrupt pin groups on R-Car V4M, - Miscellaneous fixes and improvements. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2 parents 782b72a + cd27553 commit dbe0ed3

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+142
-14
lines changed

3 files changed

+142
-14
lines changed

‎Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -120,7 +120,9 @@ additionalProperties:
120120
slew-rate: true
121121
gpio-hog: true
122122
gpios: true
123+
input: true
123124
input-enable: true
125+
output-enable: true
124126
output-high: true
125127
output-low: true
126128
line-name: true

‎drivers/pinctrl/renesas/pfc-r8a779h0.c

Lines changed: 124 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -75,10 +75,10 @@
7575
#define GPSR0_9 F_(MSIOF5_SYNC, IP1SR0_7_4)
7676
#define GPSR0_8 F_(MSIOF5_SS1, IP1SR0_3_0)
7777
#define GPSR0_7 F_(MSIOF5_SS2, IP0SR0_31_28)
78-
#define GPSR0_6 F_(IRQ0, IP0SR0_27_24)
79-
#define GPSR0_5 F_(IRQ1, IP0SR0_23_20)
80-
#define GPSR0_4 F_(IRQ2, IP0SR0_19_16)
81-
#define GPSR0_3 F_(IRQ3, IP0SR0_15_12)
78+
#define GPSR0_6 F_(IRQ0_A, IP0SR0_27_24)
79+
#define GPSR0_5 F_(IRQ1_A, IP0SR0_23_20)
80+
#define GPSR0_4 F_(IRQ2_A, IP0SR0_19_16)
81+
#define GPSR0_3 F_(IRQ3_A, IP0SR0_15_12)
8282
#define GPSR0_2 F_(GP0_02, IP0SR0_11_8)
8383
#define GPSR0_1 F_(GP0_01, IP0SR0_7_4)
8484
#define GPSR0_0 F_(GP0_00, IP0SR0_3_0)
@@ -265,10 +265,10 @@
265265
#define IP0SR0_3_0 F_(0, 0) FM(ERROROUTC_N_B) FM(TCLK2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
266266
#define IP0SR0_7_4 F_(0, 0) FM(MSIOF3_SS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
267267
#define IP0SR0_11_8 F_(0, 0) FM(MSIOF3_SS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
268-
#define IP0SR0_15_12 FM(IRQ3) FM(MSIOF3_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
269-
#define IP0SR0_19_16 FM(IRQ2) FM(MSIOF3_TXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
270-
#define IP0SR0_23_20 FM(IRQ1) FM(MSIOF3_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
271-
#define IP0SR0_27_24 FM(IRQ0) FM(MSIOF3_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
268+
#define IP0SR0_15_12 FM(IRQ3_A) FM(MSIOF3_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
269+
#define IP0SR0_19_16 FM(IRQ2_A) FM(MSIOF3_TXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
270+
#define IP0SR0_23_20 FM(IRQ1_A) FM(MSIOF3_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
271+
#define IP0SR0_27_24 FM(IRQ0_A) FM(MSIOF3_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
272272
#define IP0SR0_31_28 FM(MSIOF5_SS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
273273

274274
/* IP1SR0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
@@ -672,16 +672,16 @@ static const u16 pinmux_data[] = {
672672

673673
PINMUX_IPSR_GPSR(IP0SR0_11_8, MSIOF3_SS2),
674674

675-
PINMUX_IPSR_GPSR(IP0SR0_15_12, IRQ3),
675+
PINMUX_IPSR_GPSR(IP0SR0_15_12, IRQ3_A),
676676
PINMUX_IPSR_GPSR(IP0SR0_15_12, MSIOF3_SCK),
677677

678-
PINMUX_IPSR_GPSR(IP0SR0_19_16, IRQ2),
678+
PINMUX_IPSR_GPSR(IP0SR0_19_16, IRQ2_A),
679679
PINMUX_IPSR_GPSR(IP0SR0_19_16, MSIOF3_TXD),
680680

681-
PINMUX_IPSR_GPSR(IP0SR0_23_20, IRQ1),
681+
PINMUX_IPSR_GPSR(IP0SR0_23_20, IRQ1_A),
682682
PINMUX_IPSR_GPSR(IP0SR0_23_20, MSIOF3_RXD),
683683

684-
PINMUX_IPSR_GPSR(IP0SR0_27_24, IRQ0),
684+
PINMUX_IPSR_GPSR(IP0SR0_27_24, IRQ0_A),
685685
PINMUX_IPSR_GPSR(IP0SR0_27_24, MSIOF3_SYNC),
686686

687687
PINMUX_IPSR_GPSR(IP0SR0_31_28, MSIOF5_SS2),
@@ -1660,6 +1660,90 @@ static const unsigned int i2c3_mux[] = {
16601660
SDA3_MARK, SCL3_MARK,
16611661
};
16621662

1663+
/* - INTC-EX ---------------------------------------------------------------- */
1664+
static const unsigned int intc_ex_irq0_a_pins[] = {
1665+
/* IRQ0_A */
1666+
RCAR_GP_PIN(0, 6),
1667+
};
1668+
static const unsigned int intc_ex_irq0_a_mux[] = {
1669+
IRQ0_A_MARK,
1670+
};
1671+
static const unsigned int intc_ex_irq0_b_pins[] = {
1672+
/* IRQ0_B */
1673+
RCAR_GP_PIN(1, 20),
1674+
};
1675+
static const unsigned int intc_ex_irq0_b_mux[] = {
1676+
IRQ0_B_MARK,
1677+
};
1678+
1679+
static const unsigned int intc_ex_irq1_a_pins[] = {
1680+
/* IRQ1_A */
1681+
RCAR_GP_PIN(0, 5),
1682+
};
1683+
static const unsigned int intc_ex_irq1_a_mux[] = {
1684+
IRQ1_A_MARK,
1685+
};
1686+
static const unsigned int intc_ex_irq1_b_pins[] = {
1687+
/* IRQ1_B */
1688+
RCAR_GP_PIN(1, 21),
1689+
};
1690+
static const unsigned int intc_ex_irq1_b_mux[] = {
1691+
IRQ1_B_MARK,
1692+
};
1693+
1694+
static const unsigned int intc_ex_irq2_a_pins[] = {
1695+
/* IRQ2_A */
1696+
RCAR_GP_PIN(0, 4),
1697+
};
1698+
static const unsigned int intc_ex_irq2_a_mux[] = {
1699+
IRQ2_A_MARK,
1700+
};
1701+
static const unsigned int intc_ex_irq2_b_pins[] = {
1702+
/* IRQ2_B */
1703+
RCAR_GP_PIN(0, 13),
1704+
};
1705+
static const unsigned int intc_ex_irq2_b_mux[] = {
1706+
IRQ2_B_MARK,
1707+
};
1708+
1709+
static const unsigned int intc_ex_irq3_a_pins[] = {
1710+
/* IRQ3_A */
1711+
RCAR_GP_PIN(0, 3),
1712+
};
1713+
static const unsigned int intc_ex_irq3_a_mux[] = {
1714+
IRQ3_A_MARK,
1715+
};
1716+
static const unsigned int intc_ex_irq3_b_pins[] = {
1717+
/* IRQ3_B */
1718+
RCAR_GP_PIN(1, 23),
1719+
};
1720+
static const unsigned int intc_ex_irq3_b_mux[] = {
1721+
IRQ3_B_MARK,
1722+
};
1723+
1724+
static const unsigned int intc_ex_irq4_a_pins[] = {
1725+
/* IRQ4_A */
1726+
RCAR_GP_PIN(1, 17),
1727+
};
1728+
static const unsigned int intc_ex_irq4_a_mux[] = {
1729+
IRQ4_A_MARK,
1730+
};
1731+
static const unsigned int intc_ex_irq4_b_pins[] = {
1732+
/* IRQ4_B */
1733+
RCAR_GP_PIN(2, 3),
1734+
};
1735+
static const unsigned int intc_ex_irq4_b_mux[] = {
1736+
IRQ4_B_MARK,
1737+
};
1738+
1739+
static const unsigned int intc_ex_irq5_pins[] = {
1740+
/* IRQ5 */
1741+
RCAR_GP_PIN(2, 2),
1742+
};
1743+
static const unsigned int intc_ex_irq5_mux[] = {
1744+
IRQ5_MARK,
1745+
};
1746+
16631747
/* - MMC -------------------------------------------------------------------- */
16641748
static const unsigned int mmc_data_pins[] = {
16651749
/* MMC_SD_D[0:3], MMC_D[4:7] */
@@ -2416,6 +2500,18 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
24162500
SH_PFC_PIN_GROUP(i2c2),
24172501
SH_PFC_PIN_GROUP(i2c3),
24182502

2503+
SH_PFC_PIN_GROUP(intc_ex_irq0_a),
2504+
SH_PFC_PIN_GROUP(intc_ex_irq0_b),
2505+
SH_PFC_PIN_GROUP(intc_ex_irq1_a),
2506+
SH_PFC_PIN_GROUP(intc_ex_irq1_b),
2507+
SH_PFC_PIN_GROUP(intc_ex_irq2_a),
2508+
SH_PFC_PIN_GROUP(intc_ex_irq2_b),
2509+
SH_PFC_PIN_GROUP(intc_ex_irq3_a),
2510+
SH_PFC_PIN_GROUP(intc_ex_irq3_b),
2511+
SH_PFC_PIN_GROUP(intc_ex_irq4_a),
2512+
SH_PFC_PIN_GROUP(intc_ex_irq4_b),
2513+
SH_PFC_PIN_GROUP(intc_ex_irq5),
2514+
24192515
BUS_DATA_PIN_GROUP(mmc_data, 1),
24202516
BUS_DATA_PIN_GROUP(mmc_data, 4),
24212517
BUS_DATA_PIN_GROUP(mmc_data, 8),
@@ -2629,6 +2725,20 @@ static const char * const i2c3_groups[] = {
26292725
"i2c3",
26302726
};
26312727

2728+
static const char * const intc_ex_groups[] = {
2729+
"intc_ex_irq0_a",
2730+
"intc_ex_irq0_b",
2731+
"intc_ex_irq1_a",
2732+
"intc_ex_irq1_b",
2733+
"intc_ex_irq2_a",
2734+
"intc_ex_irq2_b",
2735+
"intc_ex_irq3_a",
2736+
"intc_ex_irq3_b",
2737+
"intc_ex_irq4_a",
2738+
"intc_ex_irq4_b",
2739+
"intc_ex_irq5",
2740+
};
2741+
26322742
static const char * const mmc_groups[] = {
26332743
"mmc_data1",
26342744
"mmc_data4",
@@ -2813,6 +2923,8 @@ static const struct sh_pfc_function pinmux_functions[] = {
28132923
SH_PFC_FUNCTION(i2c2),
28142924
SH_PFC_FUNCTION(i2c3),
28152925

2926+
SH_PFC_FUNCTION(intc_ex),
2927+
28162928
SH_PFC_FUNCTION(mmc),
28172929

28182930
SH_PFC_FUNCTION(msiof0),

‎drivers/pinctrl/renesas/pinctrl-rzg2l.c

Lines changed: 16 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -892,6 +892,8 @@ static int rzg2l_set_power_source(struct rzg2l_pinctrl *pctrl, u32 pin, u32 caps
892892
val = PVDD_1800;
893893
break;
894894
case 2500:
895+
if (!(caps & (PIN_CFG_IO_VMC_ETH0 | PIN_CFG_IO_VMC_ETH1)))
896+
return -EINVAL;
895897
val = PVDD_2500;
896898
break;
897899
case 3300:
@@ -2045,7 +2047,9 @@ static void rzg2l_gpio_irq_restore(struct rzg2l_pinctrl *pctrl)
20452047

20462048
for (unsigned int i = 0; i < RZG2L_TINT_MAX_INTERRUPT; i++) {
20472049
struct irq_data *data;
2050+
unsigned long flags;
20482051
unsigned int virq;
2052+
int ret;
20492053

20502054
if (!pctrl->hwirq[i])
20512055
continue;
@@ -2063,8 +2067,18 @@ static void rzg2l_gpio_irq_restore(struct rzg2l_pinctrl *pctrl)
20632067
continue;
20642068
}
20652069

2066-
if (!irqd_irq_disabled(data))
2070+
/*
2071+
* This has to be atomically executed to protect against a concurrent
2072+
* interrupt.
2073+
*/
2074+
raw_spin_lock_irqsave(&pctrl->lock.rlock, flags);
2075+
ret = rzg2l_gpio_irq_set_type(data, irqd_get_trigger_type(data));
2076+
if (!ret && !irqd_irq_disabled(data))
20672077
rzg2l_gpio_irq_enable(data);
2078+
raw_spin_unlock_irqrestore(&pctrl->lock.rlock, flags);
2079+
2080+
if (ret)
2081+
dev_crit(pctrl->dev, "Failed to set IRQ type for virq=%u\n", virq);
20682082
}
20692083
}
20702084

@@ -2502,7 +2516,7 @@ static void rzg2l_pinctrl_pm_setup_dedicated_regs(struct rzg2l_pinctrl *pctrl, b
25022516
}
25032517
}
25042518

2505-
static void rzg2l_pinctrl_pm_setup_pfc(struct rzg2l_pinctrl *pctrl)
2519+
static void rzg2l_pinctrl_pm_setup_pfc(struct rzg2l_pinctrl *pctrl)
25062520
{
25072521
u32 nports = pctrl->data->n_port_pins / RZG2L_PINS_PER_PORT;
25082522
const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg;

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