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Marc Zyngierdlezcano
Marc Zyngier
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dlezcano
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clocksource/drivers/arm_arch_timer: Drop CNT*_TVAL read accessors
The arch timer driver never reads the various TVAL registers, only writes to them. It is thus pointless to provide accessors for them and to implement errata workarounds. Drop these read-side accessors, and add a couple of BUG() statements for the time being. These statements will be removed further down the line. Reviewed-by: Oliver Upton <oupton@google.com> Reviewed-by: Mark Rutland <mark.rutland@arm.com> Tested-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20211017124225.3018098-3-maz@kernel.org Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
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-67
lines changed

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‎arch/arm/include/asm/arch_timer.h

-6
Original file line numberDiff line numberDiff line change
@@ -65,9 +65,6 @@ u32 arch_timer_reg_read_cp15(int access, enum arch_timer_reg reg)
6565
case ARCH_TIMER_REG_CTRL:
6666
asm volatile("mrc p15, 0, %0, c14, c2, 1" : "=r" (val));
6767
break;
68-
case ARCH_TIMER_REG_TVAL:
69-
asm volatile("mrc p15, 0, %0, c14, c2, 0" : "=r" (val));
70-
break;
7168
default:
7269
BUILD_BUG();
7370
}
@@ -76,9 +73,6 @@ u32 arch_timer_reg_read_cp15(int access, enum arch_timer_reg reg)
7673
case ARCH_TIMER_REG_CTRL:
7774
asm volatile("mrc p15, 0, %0, c14, c3, 1" : "=r" (val));
7875
break;
79-
case ARCH_TIMER_REG_TVAL:
80-
asm volatile("mrc p15, 0, %0, c14, c3, 0" : "=r" (val));
81-
break;
8276
default:
8377
BUILD_BUG();
8478
}

‎arch/arm64/include/asm/arch_timer.h

-17
Original file line numberDiff line numberDiff line change
@@ -52,8 +52,6 @@ struct arch_timer_erratum_workaround {
5252
enum arch_timer_erratum_match_type match_type;
5353
const void *id;
5454
const char *desc;
55-
u32 (*read_cntp_tval_el0)(void);
56-
u32 (*read_cntv_tval_el0)(void);
5755
u64 (*read_cntpct_el0)(void);
5856
u64 (*read_cntvct_el0)(void);
5957
int (*set_next_event_phys)(unsigned long, struct clock_event_device *);
@@ -64,17 +62,6 @@ struct arch_timer_erratum_workaround {
6462
DECLARE_PER_CPU(const struct arch_timer_erratum_workaround *,
6563
timer_unstable_counter_workaround);
6664

67-
/* inline sysreg accessors that make erratum_handler() work */
68-
static inline notrace u32 arch_timer_read_cntp_tval_el0(void)
69-
{
70-
return read_sysreg(cntp_tval_el0);
71-
}
72-
73-
static inline notrace u32 arch_timer_read_cntv_tval_el0(void)
74-
{
75-
return read_sysreg(cntv_tval_el0);
76-
}
77-
7865
static inline notrace u64 arch_timer_read_cntpct_el0(void)
7966
{
8067
return read_sysreg(cntpct_el0);
@@ -140,17 +127,13 @@ u32 arch_timer_reg_read_cp15(int access, enum arch_timer_reg reg)
140127
switch (reg) {
141128
case ARCH_TIMER_REG_CTRL:
142129
return read_sysreg(cntp_ctl_el0);
143-
case ARCH_TIMER_REG_TVAL:
144-
return arch_timer_reg_read_stable(cntp_tval_el0);
145130
default:
146131
BUILD_BUG();
147132
}
148133
} else if (access == ARCH_TIMER_VIRT_ACCESS) {
149134
switch (reg) {
150135
case ARCH_TIMER_REG_CTRL:
151136
return read_sysreg(cntv_ctl_el0);
152-
case ARCH_TIMER_REG_TVAL:
153-
return arch_timer_reg_read_stable(cntv_tval_el0);
154137
default:
155138
BUILD_BUG();
156139
}

‎drivers/clocksource/arm_arch_timer.c

-44
Original file line numberDiff line numberDiff line change
@@ -144,9 +144,6 @@ u32 arch_timer_reg_read(int access, enum arch_timer_reg reg,
144144
case ARCH_TIMER_REG_CTRL:
145145
val = readl_relaxed(timer->base + CNTP_CTL);
146146
break;
147-
case ARCH_TIMER_REG_TVAL:
148-
val = readl_relaxed(timer->base + CNTP_TVAL);
149-
break;
150147
default:
151148
BUILD_BUG();
152149
}
@@ -156,9 +153,6 @@ u32 arch_timer_reg_read(int access, enum arch_timer_reg reg,
156153
case ARCH_TIMER_REG_CTRL:
157154
val = readl_relaxed(timer->base + CNTV_CTL);
158155
break;
159-
case ARCH_TIMER_REG_TVAL:
160-
val = readl_relaxed(timer->base + CNTV_TVAL);
161-
break;
162156
default:
163157
BUILD_BUG();
164158
}
@@ -247,16 +241,6 @@ struct ate_acpi_oem_info {
247241
_new; \
248242
})
249243

250-
static u32 notrace fsl_a008585_read_cntp_tval_el0(void)
251-
{
252-
return __fsl_a008585_read_reg(cntp_tval_el0);
253-
}
254-
255-
static u32 notrace fsl_a008585_read_cntv_tval_el0(void)
256-
{
257-
return __fsl_a008585_read_reg(cntv_tval_el0);
258-
}
259-
260244
static u64 notrace fsl_a008585_read_cntpct_el0(void)
261245
{
262246
return __fsl_a008585_read_reg(cntpct_el0);
@@ -293,16 +277,6 @@ static u64 notrace fsl_a008585_read_cntvct_el0(void)
293277
_new; \
294278
})
295279

296-
static u32 notrace hisi_161010101_read_cntp_tval_el0(void)
297-
{
298-
return __hisi_161010101_read_reg(cntp_tval_el0);
299-
}
300-
301-
static u32 notrace hisi_161010101_read_cntv_tval_el0(void)
302-
{
303-
return __hisi_161010101_read_reg(cntv_tval_el0);
304-
}
305-
306280
static u64 notrace hisi_161010101_read_cntpct_el0(void)
307281
{
308282
return __hisi_161010101_read_reg(cntpct_el0);
@@ -387,16 +361,6 @@ static u64 notrace sun50i_a64_read_cntvct_el0(void)
387361
{
388362
return __sun50i_a64_read_reg(cntvct_el0);
389363
}
390-
391-
static u32 notrace sun50i_a64_read_cntp_tval_el0(void)
392-
{
393-
return read_sysreg(cntp_cval_el0) - sun50i_a64_read_cntpct_el0();
394-
}
395-
396-
static u32 notrace sun50i_a64_read_cntv_tval_el0(void)
397-
{
398-
return read_sysreg(cntv_cval_el0) - sun50i_a64_read_cntvct_el0();
399-
}
400364
#endif
401365

402366
#ifdef CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND
@@ -446,8 +410,6 @@ static const struct arch_timer_erratum_workaround ool_workarounds[] = {
446410
.match_type = ate_match_dt,
447411
.id = "fsl,erratum-a008585",
448412
.desc = "Freescale erratum a005858",
449-
.read_cntp_tval_el0 = fsl_a008585_read_cntp_tval_el0,
450-
.read_cntv_tval_el0 = fsl_a008585_read_cntv_tval_el0,
451413
.read_cntpct_el0 = fsl_a008585_read_cntpct_el0,
452414
.read_cntvct_el0 = fsl_a008585_read_cntvct_el0,
453415
.set_next_event_phys = erratum_set_next_event_tval_phys,
@@ -459,8 +421,6 @@ static const struct arch_timer_erratum_workaround ool_workarounds[] = {
459421
.match_type = ate_match_dt,
460422
.id = "hisilicon,erratum-161010101",
461423
.desc = "HiSilicon erratum 161010101",
462-
.read_cntp_tval_el0 = hisi_161010101_read_cntp_tval_el0,
463-
.read_cntv_tval_el0 = hisi_161010101_read_cntv_tval_el0,
464424
.read_cntpct_el0 = hisi_161010101_read_cntpct_el0,
465425
.read_cntvct_el0 = hisi_161010101_read_cntvct_el0,
466426
.set_next_event_phys = erratum_set_next_event_tval_phys,
@@ -470,8 +430,6 @@ static const struct arch_timer_erratum_workaround ool_workarounds[] = {
470430
.match_type = ate_match_acpi_oem_info,
471431
.id = hisi_161010101_oem_info,
472432
.desc = "HiSilicon erratum 161010101",
473-
.read_cntp_tval_el0 = hisi_161010101_read_cntp_tval_el0,
474-
.read_cntv_tval_el0 = hisi_161010101_read_cntv_tval_el0,
475433
.read_cntpct_el0 = hisi_161010101_read_cntpct_el0,
476434
.read_cntvct_el0 = hisi_161010101_read_cntvct_el0,
477435
.set_next_event_phys = erratum_set_next_event_tval_phys,
@@ -492,8 +450,6 @@ static const struct arch_timer_erratum_workaround ool_workarounds[] = {
492450
.match_type = ate_match_dt,
493451
.id = "allwinner,erratum-unknown1",
494452
.desc = "Allwinner erratum UNKNOWN1",
495-
.read_cntp_tval_el0 = sun50i_a64_read_cntp_tval_el0,
496-
.read_cntv_tval_el0 = sun50i_a64_read_cntv_tval_el0,
497453
.read_cntpct_el0 = sun50i_a64_read_cntpct_el0,
498454
.read_cntvct_el0 = sun50i_a64_read_cntvct_el0,
499455
.set_next_event_phys = erratum_set_next_event_tval_phys,

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