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ricardonrafaeljw
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x86/cpu: Add definitions for the Intel Hardware Feedback Interface
Add the CPUID feature bit and the model-specific registers needed to identify and configure the Intel Hardware Feedback Interface. Acked-by: Borislav Petkov <bp@suse.de> Signed-off-by: Ricardo Neri <ricardo.neri-calderon@linux.intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
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arch/x86/include/asm/cpufeatures.h

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#define X86_FEATURE_HWP_ACT_WINDOW (14*32+ 9) /* HWP Activity Window */
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#define X86_FEATURE_HWP_EPP (14*32+10) /* HWP Energy Perf. Preference */
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#define X86_FEATURE_HWP_PKG_REQ (14*32+11) /* HWP Package Level Request */
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#define X86_FEATURE_HFI (14*32+19) /* Hardware Feedback Interface */
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/* AMD SVM Feature Identification, CPUID level 0x8000000a (EDX), word 15 */
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#define X86_FEATURE_NPT (15*32+ 0) /* Nested Page Table support */

arch/x86/include/asm/msr-index.h

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#define PACKAGE_THERM_STATUS_PROCHOT (1 << 0)
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#define PACKAGE_THERM_STATUS_POWER_LIMIT (1 << 10)
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#define PACKAGE_THERM_STATUS_HFI_UPDATED (1 << 26)
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#define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x000001b2
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#define PACKAGE_THERM_INT_HIGH_ENABLE (1 << 0)
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#define PACKAGE_THERM_INT_LOW_ENABLE (1 << 1)
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#define PACKAGE_THERM_INT_PLN_ENABLE (1 << 24)
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#define PACKAGE_THERM_INT_HFI_ENABLE (1 << 25)
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/* Thermal Thresholds Support */
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#define THERM_INT_THRESHOLD0_ENABLE (1 << 15)
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#define MSR_VM_IGNNE 0xc0010115
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#define MSR_VM_HSAVE_PA 0xc0010117
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/* Hardware Feedback Interface */
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#define MSR_IA32_HW_FEEDBACK_PTR 0x17d0
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#define MSR_IA32_HW_FEEDBACK_CONFIG 0x17d1
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#endif /* _ASM_X86_MSR_INDEX_H */

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