Skip to content

Commit 2c00c06

Browse files
GateworksShawn Guo
Gateworks
authored and
Shawn Guo
committed
arm64: dts: freescale: Add imx8mp-venice-gw71xx-2x
The Gateworks imx8mp-venice-gw71xx-2x consists of a SOM + baseboard. The GW702x SOM contains the following: - i.MX8M Plus SoC - LPDDR4 memory - eMMC Boot device - Gateworks System Controller (GSC) with integrated EEPROM, button controller, and ADC's - PMIC - SOM connector providing: - eQoS GbE MII - 1x SPI - 2x I2C - 4x UART - 2x USB 3.0 - 1x PCI - 1x SDIO (4-bit 3.3V) - 1x SDIO (4-bit 3.3V/1.8V) - GPIO The GW71xx Baseboard contains the following: - GPS - RJ45 GbE (eQoS) - off-board I/O connector with UART, I2C, SPI, GPIO - EERPOM - PCIe clock generator - full-length miniPCIe socket with PCI/USB3 (via mux) and USB2.0 - USB Type-C with USB 2.0 host and peripheral support - Wide range DC input supply Signed-off-by: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
1 parent 7e1894e commit 2c00c06

File tree

3 files changed

+256
-0
lines changed

3 files changed

+256
-0
lines changed

‎arch/arm64/boot/dts/freescale/Makefile

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -101,6 +101,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mp-icore-mx8mp-edimm2.2.dtb
101101
dtb-$(CONFIG_ARCH_MXC) += imx8mp-msc-sm2s-ep1.dtb
102102
dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-rdk.dtb
103103
dtb-$(CONFIG_ARCH_MXC) += imx8mp-tqma8mpql-mba8mpxl.dtb
104+
dtb-$(CONFIG_ARCH_MXC) += imx8mp-venice-gw71xx-2x.dtb
104105
dtb-$(CONFIG_ARCH_MXC) += imx8mp-venice-gw74xx.dtb
105106
dtb-$(CONFIG_ARCH_MXC) += imx8mp-venice-gw7905-2x.dtb
106107
dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-nonwifi-dahlia.dtb

‎arch/arm64/boot/dts/freescale/imx8mp-venice-gw71xx-2x.dts

Lines changed: 19 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,19 @@
1+
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2+
/*
3+
* Copyright 2023 Gateworks Corporation
4+
*/
5+
6+
/dts-v1/;
7+
8+
#include "imx8mp.dtsi"
9+
#include "imx8mp-venice-gw702x.dtsi"
10+
#include "imx8mp-venice-gw71xx.dtsi"
11+
12+
/ {
13+
model = "Gateworks Venice GW71xx-2x i.MX8MP Development Kit";
14+
compatible = "gateworks,imx8mp-gw71xx-2x", "fsl,imx8mp";
15+
16+
chosen {
17+
stdout-path = &uart2;
18+
};
19+
};

‎arch/arm64/boot/dts/freescale/imx8mp-venice-gw71xx.dtsi

Lines changed: 236 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,236 @@
1+
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2+
/*
3+
* Copyright 2023 Gateworks Corporation
4+
*/
5+
6+
#include <dt-bindings/gpio/gpio.h>
7+
#include <dt-bindings/leds/common.h>
8+
#include <dt-bindings/phy/phy-imx8-pcie.h>
9+
10+
/ {
11+
led-controller {
12+
compatible = "gpio-leds";
13+
pinctrl-names = "default";
14+
pinctrl-0 = <&pinctrl_gpio_leds>;
15+
16+
led-0 {
17+
function = LED_FUNCTION_STATUS;
18+
color = <LED_COLOR_ID_GREEN>;
19+
gpios = <&gpio4 1 GPIO_ACTIVE_HIGH>;
20+
default-state = "on";
21+
linux,default-trigger = "heartbeat";
22+
};
23+
24+
led-1 {
25+
function = LED_FUNCTION_STATUS;
26+
color = <LED_COLOR_ID_RED>;
27+
gpios = <&gpio4 5 GPIO_ACTIVE_HIGH>;
28+
default-state = "off";
29+
};
30+
};
31+
32+
pcie0_refclk: clock-pcie0 {
33+
compatible = "fixed-clock";
34+
#clock-cells = <0>;
35+
clock-frequency = <100000000>;
36+
};
37+
38+
pps {
39+
compatible = "pps-gpio";
40+
pinctrl-names = "default";
41+
pinctrl-0 = <&pinctrl_pps>;
42+
gpios = <&gpio4 3 GPIO_ACTIVE_HIGH>;
43+
status = "okay";
44+
};
45+
};
46+
47+
/* off-board header */
48+
&ecspi2 {
49+
pinctrl-names = "default";
50+
pinctrl-0 = <&pinctrl_spi2>;
51+
cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
52+
status = "okay";
53+
};
54+
55+
&gpio4 {
56+
gpio-line-names =
57+
"", "", "", "",
58+
"", "", "", "",
59+
"dio1", "", "", "dio0",
60+
"", "", "pci_usb_sel", "",
61+
"", "", "", "",
62+
"", "", "", "",
63+
"dio3", "", "dio2", "",
64+
"pci_wdis#", "", "", "";
65+
};
66+
67+
&i2c2 {
68+
clock-frequency = <400000>;
69+
pinctrl-names = "default";
70+
pinctrl-0 = <&pinctrl_i2c2>;
71+
status = "okay";
72+
73+
accelerometer@19 {
74+
compatible = "st,lis2de12";
75+
reg = <0x19>;
76+
pinctrl-names = "default";
77+
pinctrl-0 = <&pinctrl_accel>;
78+
st,drdy-int-pin = <1>;
79+
interrupt-parent = <&gpio4>;
80+
interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
81+
interrupt-names = "INT1";
82+
};
83+
};
84+
85+
&pcie_phy {
86+
fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
87+
fsl,clkreq-unsupported;
88+
clocks = <&pcie0_refclk>;
89+
clock-names = "ref";
90+
status = "okay";
91+
};
92+
93+
&pcie {
94+
pinctrl-names = "default";
95+
pinctrl-0 = <&pinctrl_pcie0>;
96+
reset-gpio = <&gpio4 29 GPIO_ACTIVE_LOW>;
97+
status = "okay";
98+
};
99+
100+
/* GPS */
101+
&uart1 {
102+
pinctrl-names = "default";
103+
pinctrl-0 = <&pinctrl_uart1>;
104+
status = "okay";
105+
};
106+
107+
/* off-board header */
108+
&uart3 {
109+
pinctrl-names = "default";
110+
pinctrl-0 = <&pinctrl_uart3>;
111+
status = "okay";
112+
};
113+
114+
/* USB1 Type-C front panel */
115+
&usb3_0 {
116+
pinctrl-names = "default";
117+
pinctrl-0 = <&pinctrl_usb1>;
118+
fsl,over-current-active-low;
119+
status = "okay";
120+
};
121+
122+
&usb3_phy0 {
123+
status = "okay";
124+
};
125+
126+
&usb_dwc3_0 {
127+
/* dual role is implemented but not a full featured OTG */
128+
adp-disable;
129+
hnp-disable;
130+
srp-disable;
131+
dr_mode = "otg";
132+
usb-role-switch;
133+
role-switch-default-mode = "peripheral";
134+
status = "okay";
135+
136+
connector {
137+
compatible = "gpio-usb-b-connector", "usb-b-connector";
138+
pinctrl-names = "default";
139+
pinctrl-0 = <&pinctrl_usbcon1>;
140+
type = "micro";
141+
label = "Type-C";
142+
id-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>;
143+
};
144+
};
145+
146+
/* USB2 - MiniPCIe socket */
147+
&usb3_1 {
148+
fsl,permanently-attached;
149+
fsl,disable-port-power-control;
150+
status = "okay";
151+
};
152+
153+
&usb3_phy1 {
154+
status = "okay";
155+
};
156+
157+
&usb_dwc3_1 {
158+
dr_mode = "host";
159+
status = "okay";
160+
};
161+
162+
&iomuxc {
163+
pinctrl-names = "default";
164+
pinctrl-0 = <&pinctrl_hog>;
165+
166+
pinctrl_hog: hoggrp {
167+
fsl,pins = <
168+
MX8MP_IOMUXC_SAI1_RXD6__GPIO4_IO08 0x40000146 /* DIO1 */
169+
MX8MP_IOMUXC_SAI1_TXC__GPIO4_IO11 0x40000146 /* DIO0 */
170+
MX8MP_IOMUXC_SAI1_TXD2__GPIO4_IO14 0x40000106 /* PCIE_USBSEL */
171+
MX8MP_IOMUXC_SAI2_TXD0__GPIO4_IO26 0x40000146 /* DIO2 */
172+
MX8MP_IOMUXC_SAI2_TXFS__GPIO4_IO24 0x40000146 /* DIO3 */
173+
MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x40000106 /* PCIE_WDIS# */
174+
>;
175+
};
176+
177+
pinctrl_accel: accelgrp {
178+
fsl,pins = <
179+
MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21 0x150 /* IRQ */
180+
>;
181+
};
182+
183+
pinctrl_gpio_leds: gpioledgrp {
184+
fsl,pins = <
185+
MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x6 /* LEDG */
186+
MX8MP_IOMUXC_SAI1_RXD3__GPIO4_IO05 0x6 /* LEDR */
187+
>;
188+
};
189+
190+
pinctrl_pcie0: pcie0grp {
191+
fsl,pins = <
192+
MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x106
193+
>;
194+
};
195+
196+
pinctrl_pps: ppsgrp {
197+
fsl,pins = <
198+
MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x146
199+
>;
200+
};
201+
202+
pinctrl_usb1: usb1grp {
203+
fsl,pins = <
204+
MX8MP_IOMUXC_GPIO1_IO13__USB1_OTG_OC 0x140 /* USB1_FLT# */
205+
>;
206+
};
207+
208+
pinctrl_usbcon1: usbcon1grp {
209+
fsl,pins = <
210+
MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x140 /* USB1_ID */
211+
>;
212+
};
213+
214+
pinctrl_spi2: spi2grp {
215+
fsl,pins = <
216+
MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x140
217+
MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x140
218+
MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x140
219+
MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x140
220+
>;
221+
};
222+
223+
pinctrl_uart1: uart1grp {
224+
fsl,pins = <
225+
MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140
226+
MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140
227+
>;
228+
};
229+
230+
pinctrl_uart3: uart3grp {
231+
fsl,pins = <
232+
MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x140
233+
MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x140
234+
>;
235+
};
236+
};

0 commit comments

Comments
 (0)