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Merge branch 'pm-cpufreq'
Merge cpufreq updates for 6.10: - Rework the handling of disabled turbo in the intel_pstate driver and make it update the maximum CPU frequency consistently regardless of the reason on top of a number of cleanups (Rafael Wysocki). - Add missing checks for NULL .exit() cpufreq driver callback to the cpufreq core (Viresh Kumar). - Prevent pulicy->max from going above the frequency QoS maximum value when cpufreq_frequency_table_verify() is used (Xuewen Yan). - Prevent a negative CPU number or frequency value from being printed if they are really large (Joshua Yeong). - Update MAINTAINERS entry for amd-pstate to add two new submaintainers and a designated reviewer (Huang Rui). - Clean up the amd-pstate driver and update its documentation (Gautham Shenoy). - Fix the highest frequency issue in the amd-pstate driver which limits performance (Perry Yuan). - Enable CPPC v2 for certain processors in the family 17H, as requested by TR40 processor users who expect improved performance and lower system temperature (Perry Yuan). - Change latency and delay values to be read from platform firmware firstly for more accurate timing (Perry Yuan). - A new quirk is introduced for supporting amd-pstate on legacy processors which either lack CPPC capability, or only only have CPPC v2 capability (Perry Yuan). - Sun50i: Add support for opp_supported_hw, H616 platform and general cleanups (Andre Przywara, Martin Botka, Brandon Cheo Fusi, Dan Carpenter, Viresh Kumar). - CPPC: Fix possible null pointer dereference (Aleksandr Mishin). - Eliminate uses of of_node_put() (Javier Carrasco, and Shivani Gupta). - brcmstb-avs: ISO C90 forbids mixed declarations (Portia Stephens). - mediatek: Add support for MT7988A (Sam Shih). - cpufreq-qcom-hw: Add SM4450 compatibles in DT bindings (Tengfei Fan). - Fix struct cpudata::epp_cached kernel-doc in the intel_pstate cpufreq driver (Jeff Johnson). * pm-cpufreq: (46 commits) cpufreq: amd-pstate: fix the highest frequency issue which limits performance cpufreq: intel_pstate: fix struct cpudata::epp_cached kernel-doc cpufreq: Fix up printing large CPU numbers and frequency values MAINTAINERS: cpufreq: amd-pstate: Add co-maintainers and reviewer cpufreq: amd-pstate: remove unused variable lowest_nonlinear_freq cpufreq: amd-pstate: fix code format problems cpufreq: amd-pstate: Add quirk for the pstate CPPC capabilities missing cppc_acpi: print error message if CPPC is unsupported cpufreq: amd-pstate: get transition delay and latency value from ACPI tables cpufreq: amd-pstate: Bail out if min/max/nominal_freq is 0 cpufreq: amd-pstate: Remove amd_get_{min,max,nominal,lowest_nonlinear}_freq() cpufreq: amd-pstate: Unify computation of {max,min,nominal,lowest_nonlinear}_freq cpufreq: amd-pstate: Document the units for freq variables in amd_cpudata cpufreq: amd-pstate: Document *_limit_* fields in struct amd_cpudata dt-bindings: cpufreq: cpufreq-qcom-hw: Add SM4450 compatibles cpufreq: sun50i: fix error returns in dt_has_supported_hw() cpufreq: brcmstb-avs-cpufreq: ISO C90 forbids mixed declarations cpufreq: dt-platdev: eliminate uses of of_node_put() cpufreq: dt: eliminate uses of of_node_put() cpufreq: ti: Implement scope-based cleanup in ti_cpufreq_match_node() ...
2 parents eefb5db + bf202e6 commit 1444938

27 files changed

+694
-349
lines changed

‎Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml

+2
Original file line numberDiff line numberDiff line change
@@ -38,6 +38,7 @@ properties:
3838
- qcom,sc7280-cpufreq-epss
3939
- qcom,sc8280xp-cpufreq-epss
4040
- qcom,sdx75-cpufreq-epss
41+
- qcom,sm4450-cpufreq-epss
4142
- qcom,sm6375-cpufreq-epss
4243
- qcom,sm8250-cpufreq-epss
4344
- qcom,sm8350-cpufreq-epss
@@ -133,6 +134,7 @@ allOf:
133134
- qcom,sc8280xp-cpufreq-epss
134135
- qcom,sdm670-cpufreq-hw
135136
- qcom,sdm845-cpufreq-hw
137+
- qcom,sm4450-cpufreq-epss
136138
- qcom,sm6115-cpufreq-hw
137139
- qcom,sm6350-cpufreq-hw
138140
- qcom,sm6375-cpufreq-epss

‎Documentation/devicetree/bindings/opp/allwinner,sun50i-h6-operating-points.yaml

+43-44
Original file line numberDiff line numberDiff line change
@@ -13,25 +13,25 @@ maintainers:
1313
description: |
1414
For some SoCs, the CPU frequency subset and voltage value of each
1515
OPP varies based on the silicon variant in use. Allwinner Process
16-
Voltage Scaling Tables defines the voltage and frequency value based
17-
on the speedbin blown in the efuse combination. The
18-
sun50i-cpufreq-nvmem driver reads the efuse value from the SoC to
19-
provide the OPP framework with required information.
16+
Voltage Scaling Tables define the voltage and frequency values based
17+
on the speedbin blown in the efuse combination.
2018
2119
allOf:
2220
- $ref: opp-v2-base.yaml#
2321

2422
properties:
2523
compatible:
26-
const: allwinner,sun50i-h6-operating-points
24+
enum:
25+
- allwinner,sun50i-h6-operating-points
26+
- allwinner,sun50i-h616-operating-points
2727

2828
nvmem-cells:
2929
description: |
3030
A phandle pointing to a nvmem-cells node representing the efuse
31-
registers that has information about the speedbin that is used
31+
register that has information about the speedbin that is used
3232
to select the right frequency/voltage value pair. Please refer
33-
the for nvmem-cells bindings
34-
Documentation/devicetree/bindings/nvmem/nvmem.txt and also
33+
to the nvmem-cells bindings in
34+
Documentation/devicetree/bindings/nvmem/nvmem.yaml and also the
3535
examples below.
3636
3737
opp-shared: true
@@ -47,15 +47,18 @@ patternProperties:
4747
properties:
4848
opp-hz: true
4949
clock-latency-ns: true
50+
opp-microvolt: true
51+
opp-supported-hw:
52+
maxItems: 1
53+
description:
54+
A single 32 bit bitmap value, representing compatible HW, one
55+
bit per speed bin index.
5056

5157
patternProperties:
5258
"^opp-microvolt-speed[0-9]$": true
5359

5460
required:
5561
- opp-hz
56-
- opp-microvolt-speed0
57-
- opp-microvolt-speed1
58-
- opp-microvolt-speed2
5962

6063
unevaluatedProperties: false
6164

@@ -77,58 +80,54 @@ examples:
7780
opp-microvolt-speed2 = <800000>;
7881
};
7982
80-
opp-720000000 {
83+
opp-1080000000 {
8184
clock-latency-ns = <244144>; /* 8 32k periods */
82-
opp-hz = /bits/ 64 <720000000>;
85+
opp-hz = /bits/ 64 <1080000000>;
8386
84-
opp-microvolt-speed0 = <880000>;
85-
opp-microvolt-speed1 = <820000>;
86-
opp-microvolt-speed2 = <800000>;
87+
opp-microvolt-speed0 = <1060000>;
88+
opp-microvolt-speed1 = <880000>;
89+
opp-microvolt-speed2 = <840000>;
8790
};
8891
89-
opp-816000000 {
92+
opp-1488000000 {
9093
clock-latency-ns = <244144>; /* 8 32k periods */
91-
opp-hz = /bits/ 64 <816000000>;
94+
opp-hz = /bits/ 64 <1488000000>;
9295
93-
opp-microvolt-speed0 = <880000>;
94-
opp-microvolt-speed1 = <820000>;
95-
opp-microvolt-speed2 = <800000>;
96+
opp-microvolt-speed0 = <1160000>;
97+
opp-microvolt-speed1 = <1000000>;
98+
opp-microvolt-speed2 = <960000>;
9699
};
100+
};
97101
98-
opp-888000000 {
99-
clock-latency-ns = <244144>; /* 8 32k periods */
100-
opp-hz = /bits/ 64 <888000000>;
101-
102-
opp-microvolt-speed0 = <940000>;
103-
opp-microvolt-speed1 = <820000>;
104-
opp-microvolt-speed2 = <800000>;
105-
};
102+
- |
103+
opp-table {
104+
compatible = "allwinner,sun50i-h616-operating-points";
105+
nvmem-cells = <&speedbin_efuse>;
106+
opp-shared;
106107
107-
opp-1080000000 {
108+
opp-480000000 {
108109
clock-latency-ns = <244144>; /* 8 32k periods */
109-
opp-hz = /bits/ 64 <1080000000>;
110+
opp-hz = /bits/ 64 <480000000>;
110111
111-
opp-microvolt-speed0 = <1060000>;
112-
opp-microvolt-speed1 = <880000>;
113-
opp-microvolt-speed2 = <840000>;
112+
opp-microvolt = <900000>;
113+
opp-supported-hw = <0x1f>;
114114
};
115115
116-
opp-1320000000 {
116+
opp-792000000 {
117117
clock-latency-ns = <244144>; /* 8 32k periods */
118-
opp-hz = /bits/ 64 <1320000000>;
118+
opp-hz = /bits/ 64 <792000000>;
119119
120-
opp-microvolt-speed0 = <1160000>;
121-
opp-microvolt-speed1 = <940000>;
122-
opp-microvolt-speed2 = <900000>;
120+
opp-microvolt-speed1 = <900000>;
121+
opp-microvolt-speed4 = <940000>;
122+
opp-supported-hw = <0x12>;
123123
};
124124
125-
opp-1488000000 {
125+
opp-1512000000 {
126126
clock-latency-ns = <244144>; /* 8 32k periods */
127-
opp-hz = /bits/ 64 <1488000000>;
127+
opp-hz = /bits/ 64 <1512000000>;
128128
129-
opp-microvolt-speed0 = <1160000>;
130-
opp-microvolt-speed1 = <1000000>;
131-
opp-microvolt-speed2 = <960000>;
129+
opp-microvolt = <1100000>;
130+
opp-supported-hw = <0x0a>;
132131
};
133132
};
134133

‎MAINTAINERS

+3
Original file line numberDiff line numberDiff line change
@@ -1062,6 +1062,9 @@ F: drivers/gpu/drm/amd/pm/
10621062

10631063
AMD PSTATE DRIVER
10641064
M: Huang Rui <ray.huang@amd.com>
1065+
M: Gautham R. Shenoy <gautham.shenoy@amd.com>
1066+
M: Mario Limonciello <mario.limonciello@amd.com>
1067+
R: Perry Yuan <perry.yuan@amd.com>
10651068
L: linux-pm@vger.kernel.org
10661069
S: Supported
10671070
F: Documentation/admin-guide/pm/amd-pstate.rst

‎arch/arm64/boot/dts/allwinner/sun50i-h616-bigtreetech-cb1.dtsi

+5
Original file line numberDiff line numberDiff line change
@@ -6,6 +6,7 @@
66
/dts-v1/;
77

88
#include "sun50i-h616.dtsi"
9+
#include "sun50i-h616-cpu-opp.dtsi"
910

1011
#include <dt-bindings/gpio/gpio.h>
1112
#include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -62,6 +63,10 @@
6263
};
6364
};
6465

66+
&cpu0 {
67+
cpu-supply = <&reg_dcdc2>;
68+
};
69+
6570
&mmc0 {
6671
vmmc-supply = <&reg_dldo1>;
6772
/* Card detection pin is not connected */

‎arch/arm64/boot/dts/allwinner/sun50i-h616-cpu-opp.dtsi

+115
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,115 @@
1+
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2+
// Copyright (C) 2023 Martin Botka <martin@somainline.org>
3+
4+
/ {
5+
cpu_opp_table: opp-table-cpu {
6+
compatible = "allwinner,sun50i-h616-operating-points";
7+
nvmem-cells = <&cpu_speed_grade>;
8+
opp-shared;
9+
10+
opp-480000000 {
11+
opp-hz = /bits/ 64 <480000000>;
12+
opp-microvolt = <900000>;
13+
clock-latency-ns = <244144>; /* 8 32k periods */
14+
opp-supported-hw = <0x1f>;
15+
};
16+
17+
opp-600000000 {
18+
opp-hz = /bits/ 64 <600000000>;
19+
opp-microvolt = <900000>;
20+
clock-latency-ns = <244144>; /* 8 32k periods */
21+
opp-supported-hw = <0x12>;
22+
};
23+
24+
opp-720000000 {
25+
opp-hz = /bits/ 64 <720000000>;
26+
opp-microvolt = <900000>;
27+
clock-latency-ns = <244144>; /* 8 32k periods */
28+
opp-supported-hw = <0x0d>;
29+
};
30+
31+
opp-792000000 {
32+
opp-hz = /bits/ 64 <792000000>;
33+
opp-microvolt-speed1 = <900000>;
34+
opp-microvolt-speed4 = <940000>;
35+
clock-latency-ns = <244144>; /* 8 32k periods */
36+
opp-supported-hw = <0x12>;
37+
};
38+
39+
opp-936000000 {
40+
opp-hz = /bits/ 64 <936000000>;
41+
opp-microvolt = <900000>;
42+
clock-latency-ns = <244144>; /* 8 32k periods */
43+
opp-supported-hw = <0x0d>;
44+
};
45+
46+
opp-1008000000 {
47+
opp-hz = /bits/ 64 <1008000000>;
48+
opp-microvolt-speed0 = <950000>;
49+
opp-microvolt-speed1 = <940000>;
50+
opp-microvolt-speed2 = <950000>;
51+
opp-microvolt-speed3 = <950000>;
52+
opp-microvolt-speed4 = <1020000>;
53+
clock-latency-ns = <244144>; /* 8 32k periods */
54+
opp-supported-hw = <0x1f>;
55+
};
56+
57+
opp-1104000000 {
58+
opp-hz = /bits/ 64 <1104000000>;
59+
opp-microvolt-speed0 = <1000000>;
60+
opp-microvolt-speed2 = <1000000>;
61+
opp-microvolt-speed3 = <1000000>;
62+
clock-latency-ns = <244144>; /* 8 32k periods */
63+
opp-supported-hw = <0x0d>;
64+
};
65+
66+
opp-1200000000 {
67+
opp-hz = /bits/ 64 <1200000000>;
68+
opp-microvolt-speed0 = <1050000>;
69+
opp-microvolt-speed1 = <1020000>;
70+
opp-microvolt-speed2 = <1050000>;
71+
opp-microvolt-speed3 = <1050000>;
72+
opp-microvolt-speed4 = <1100000>;
73+
clock-latency-ns = <244144>; /* 8 32k periods */
74+
opp-supported-hw = <0x1f>;
75+
};
76+
77+
opp-1320000000 {
78+
opp-hz = /bits/ 64 <1320000000>;
79+
opp-microvolt = <1100000>;
80+
clock-latency-ns = <244144>; /* 8 32k periods */
81+
opp-supported-hw = <0x1d>;
82+
};
83+
84+
opp-1416000000 {
85+
opp-hz = /bits/ 64 <1416000000>;
86+
opp-microvolt = <1100000>;
87+
clock-latency-ns = <244144>; /* 8 32k periods */
88+
opp-supported-hw = <0x0d>;
89+
};
90+
91+
opp-1512000000 {
92+
opp-hz = /bits/ 64 <1512000000>;
93+
opp-microvolt-speed1 = <1100000>;
94+
opp-microvolt-speed3 = <1100000>;
95+
clock-latency-ns = <244144>; /* 8 32k periods */
96+
opp-supported-hw = <0x0a>;
97+
};
98+
};
99+
};
100+
101+
&cpu0 {
102+
operating-points-v2 = <&cpu_opp_table>;
103+
};
104+
105+
&cpu1 {
106+
operating-points-v2 = <&cpu_opp_table>;
107+
};
108+
109+
&cpu2 {
110+
operating-points-v2 = <&cpu_opp_table>;
111+
};
112+
113+
&cpu3 {
114+
operating-points-v2 = <&cpu_opp_table>;
115+
};

‎arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts

+5
Original file line numberDiff line numberDiff line change
@@ -6,12 +6,17 @@
66
/dts-v1/;
77

88
#include "sun50i-h616-orangepi-zero.dtsi"
9+
#include "sun50i-h616-cpu-opp.dtsi"
910

1011
/ {
1112
model = "OrangePi Zero2";
1213
compatible = "xunlong,orangepi-zero2", "allwinner,sun50i-h616";
1314
};
1415

16+
&cpu0 {
17+
cpu-supply = <&reg_dcdca>;
18+
};
19+
1520
&emac0 {
1621
allwinner,rx-delay-ps = <3100>;
1722
allwinner,tx-delay-ps = <700>;

‎arch/arm64/boot/dts/allwinner/sun50i-h616-x96-mate.dts

+5
Original file line numberDiff line numberDiff line change
@@ -6,6 +6,7 @@
66
/dts-v1/;
77

88
#include "sun50i-h616.dtsi"
9+
#include "sun50i-h616-cpu-opp.dtsi"
910

1011
#include <dt-bindings/gpio/gpio.h>
1112
#include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -32,6 +33,10 @@
3233
};
3334
};
3435

36+
&cpu0 {
37+
cpu-supply = <&reg_dcdca>;
38+
};
39+
3540
&ehci0 {
3641
status = "okay";
3742
};

‎arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi

+8
Original file line numberDiff line numberDiff line change
@@ -26,6 +26,7 @@
2626
reg = <0>;
2727
enable-method = "psci";
2828
clocks = <&ccu CLK_CPUX>;
29+
#cooling-cells = <2>;
2930
};
3031

3132
cpu1: cpu@1 {
@@ -34,6 +35,7 @@
3435
reg = <1>;
3536
enable-method = "psci";
3637
clocks = <&ccu CLK_CPUX>;
38+
#cooling-cells = <2>;
3739
};
3840

3941
cpu2: cpu@2 {
@@ -42,6 +44,7 @@
4244
reg = <2>;
4345
enable-method = "psci";
4446
clocks = <&ccu CLK_CPUX>;
47+
#cooling-cells = <2>;
4548
};
4649

4750
cpu3: cpu@3 {
@@ -50,6 +53,7 @@
5053
reg = <3>;
5154
enable-method = "psci";
5255
clocks = <&ccu CLK_CPUX>;
56+
#cooling-cells = <2>;
5357
};
5458
};
5559

@@ -156,6 +160,10 @@
156160
ths_calibration: thermal-sensor-calibration@14 {
157161
reg = <0x14 0x8>;
158162
};
163+
164+
cpu_speed_grade: cpu-speed-grade@0 {
165+
reg = <0x0 2>;
166+
};
159167
};
160168

161169
watchdog: watchdog@30090a0 {

‎arch/arm64/boot/dts/allwinner/sun50i-h618-longan-module-3h.dtsi

+5
Original file line numberDiff line numberDiff line change
@@ -4,6 +4,11 @@
44
*/
55

66
#include "sun50i-h616.dtsi"
7+
#include "sun50i-h616-cpu-opp.dtsi"
8+
9+
&cpu0 {
10+
cpu-supply = <&reg_dcdc2>;
11+
};
712

813
&mmc2 {
914
pinctrl-names = "default";

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