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#define TIMER_SYNC_TICKS 3
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- /* Pointless struct to minimise diff */
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- struct _sun5i_timer {
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+ struct sun5i_timer {
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void __iomem * base ;
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struct clk * clk ;
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struct notifier_block clk_rate_cb ;
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u32 ticks_per_jiffy ;
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- };
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-
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- struct sun5i_timer {
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- struct _sun5i_timer timer ;
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struct clocksource clksrc ;
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struct clock_event_device clkevt ;
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};
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#define nb_to_sun5i_timer (x ) \
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- container_of(x, struct sun5i_timer, timer. clk_rate_cb)
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+ container_of(x, struct sun5i_timer, clk_rate_cb)
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#define clksrc_to_sun5i_timer (x ) \
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container_of(x, struct sun5i_timer, clksrc)
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#define clkevt_to_sun5i_timer (x ) \
@@ -64,36 +59,36 @@ struct sun5i_timer {
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*/
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static void sun5i_clkevt_sync (struct sun5i_timer * ce )
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{
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- u32 old = readl (ce -> timer . base + TIMER_CNTVAL_LO_REG (1 ));
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+ u32 old = readl (ce -> base + TIMER_CNTVAL_LO_REG (1 ));
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- while ((old - readl (ce -> timer . base + TIMER_CNTVAL_LO_REG (1 ))) < TIMER_SYNC_TICKS )
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+ while ((old - readl (ce -> base + TIMER_CNTVAL_LO_REG (1 ))) < TIMER_SYNC_TICKS )
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cpu_relax ();
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}
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static void sun5i_clkevt_time_stop (struct sun5i_timer * ce , u8 timer )
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{
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- u32 val = readl (ce -> timer . base + TIMER_CTL_REG (timer ));
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- writel (val & ~TIMER_CTL_ENABLE , ce -> timer . base + TIMER_CTL_REG (timer ));
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+ u32 val = readl (ce -> base + TIMER_CTL_REG (timer ));
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+ writel (val & ~TIMER_CTL_ENABLE , ce -> base + TIMER_CTL_REG (timer ));
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sun5i_clkevt_sync (ce );
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}
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static void sun5i_clkevt_time_setup (struct sun5i_timer * ce , u8 timer , u32 delay )
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{
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- writel (delay , ce -> timer . base + TIMER_INTVAL_LO_REG (timer ));
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+ writel (delay , ce -> base + TIMER_INTVAL_LO_REG (timer ));
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}
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static void sun5i_clkevt_time_start (struct sun5i_timer * ce , u8 timer , bool periodic )
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{
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- u32 val = readl (ce -> timer . base + TIMER_CTL_REG (timer ));
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+ u32 val = readl (ce -> base + TIMER_CTL_REG (timer ));
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if (periodic )
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val &= ~TIMER_CTL_ONESHOT ;
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else
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val |= TIMER_CTL_ONESHOT ;
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writel (val | TIMER_CTL_ENABLE | TIMER_CTL_RELOAD ,
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- ce -> timer . base + TIMER_CTL_REG (timer ));
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+ ce -> base + TIMER_CTL_REG (timer ));
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}
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static int sun5i_clkevt_shutdown (struct clock_event_device * clkevt )
@@ -118,7 +113,7 @@ static int sun5i_clkevt_set_periodic(struct clock_event_device *clkevt)
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struct sun5i_timer * ce = clkevt_to_sun5i_timer (clkevt );
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sun5i_clkevt_time_stop (ce , 0 );
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- sun5i_clkevt_time_setup (ce , 0 , ce -> timer . ticks_per_jiffy );
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+ sun5i_clkevt_time_setup (ce , 0 , ce -> ticks_per_jiffy );
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sun5i_clkevt_time_start (ce , 0 , true);
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return 0 ;
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}
@@ -139,7 +134,7 @@ static irqreturn_t sun5i_timer_interrupt(int irq, void *dev_id)
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{
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struct sun5i_timer * ce = dev_id ;
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- writel (0x1 , ce -> timer . base + TIMER_IRQ_ST_REG );
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+ writel (0x1 , ce -> base + TIMER_IRQ_ST_REG );
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ce -> clkevt .event_handler (& ce -> clkevt );
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return IRQ_HANDLED ;
@@ -149,7 +144,7 @@ static u64 sun5i_clksrc_read(struct clocksource *clksrc)
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{
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struct sun5i_timer * cs = clksrc_to_sun5i_timer (clksrc );
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- return ~readl (cs -> timer . base + TIMER_CNTVAL_LO_REG (1 ));
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+ return ~readl (cs -> base + TIMER_CNTVAL_LO_REG (1 ));
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}
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static int sun5i_rate_cb (struct notifier_block * nb ,
@@ -166,7 +161,7 @@ static int sun5i_rate_cb(struct notifier_block *nb,
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case POST_RATE_CHANGE :
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clocksource_register_hz (& cs -> clksrc , ndata -> new_rate );
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clockevents_update_freq (& cs -> clkevt , ndata -> new_rate );
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- cs -> timer . ticks_per_jiffy = DIV_ROUND_UP (ndata -> new_rate , HZ );
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+ cs -> ticks_per_jiffy = DIV_ROUND_UP (ndata -> new_rate , HZ );
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break ;
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default :
@@ -180,7 +175,7 @@ static int __init sun5i_setup_clocksource(struct device_node *node,
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struct sun5i_timer * cs ,
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unsigned long rate )
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{
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- void __iomem * base = cs -> timer . base ;
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+ void __iomem * base = cs -> base ;
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int ret ;
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writel (~0 , base + TIMER_INTVAL_LO_REG (1 ));
@@ -206,7 +201,7 @@ static int __init sun5i_setup_clockevent(struct device_node *node,
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struct sun5i_timer * ce ,
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unsigned long rate , int irq )
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{
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- void __iomem * base = ce -> timer . base ;
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+ void __iomem * base = ce -> base ;
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int ret ;
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u32 val ;
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@@ -282,13 +277,13 @@ static int __init sun5i_timer_init(struct device_node *node)
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goto err_disable_clk ;
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}
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- st -> timer . base = timer_base ;
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- st -> timer . ticks_per_jiffy = DIV_ROUND_UP (rate , HZ );
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- st -> timer . clk = clk ;
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- st -> timer . clk_rate_cb .notifier_call = sun5i_rate_cb ;
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- st -> timer . clk_rate_cb .next = NULL ;
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+ st -> base = timer_base ;
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+ st -> ticks_per_jiffy = DIV_ROUND_UP (rate , HZ );
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+ st -> clk = clk ;
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+ st -> clk_rate_cb .notifier_call = sun5i_rate_cb ;
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+ st -> clk_rate_cb .next = NULL ;
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- ret = clk_notifier_register (clk , & st -> timer . clk_rate_cb );
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+ ret = clk_notifier_register (clk , & st -> clk_rate_cb );
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if (ret ) {
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pr_err ("Unable to register clock notifier.\n" );
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goto err_disable_clk ;
@@ -305,7 +300,7 @@ static int __init sun5i_timer_init(struct device_node *node)
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return sun5i_setup_clockevent (node , st , rate , irq );
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err_remove_notifier :
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- clk_notifier_unregister (clk , & st -> timer . clk_rate_cb );
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+ clk_notifier_unregister (clk , & st -> clk_rate_cb );
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err_disable_clk :
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clk_disable_unprepare (clk );
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err_free :
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