|
44 | 44 | };
|
45 | 45 | };
|
46 | 46 |
|
47 |
| - pcie0_refclk: pcie0-refclk { |
48 |
| - compatible = "fixed-clock"; |
49 |
| - #clock-cells = <0>; |
50 |
| - clock-frequency = <100000000>; |
51 |
| - }; |
52 |
| - |
53 |
| - reg_pcie0: regulator-pcie { |
54 |
| - compatible = "regulator-fixed"; |
55 |
| - pinctrl-names = "default"; |
56 |
| - pinctrl-0 = <&pinctrl_pcie0_reg>; |
57 |
| - regulator-name = "MPCIE_3V3"; |
58 |
| - regulator-min-microvolt = <3300000>; |
59 |
| - regulator-max-microvolt = <3300000>; |
60 |
| - /*gpio = <&x8h7_gpio 29 GPIO_ACTIVE_HIGH>;*/ /* stm32h7 PWM6 */ |
61 |
| - enable-active-high; |
62 |
| - }; |
63 |
| - |
64 | 47 | reg_usdhc2_vmmc: regulator-usdhc2 {
|
65 | 48 | compatible = "regulator-fixed";
|
66 | 49 | pinctrl-names = "default";
|
|
266 | 249 | status = "okay";
|
267 | 250 | };
|
268 | 251 |
|
269 |
| -&pcie_phy { |
270 |
| - fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>; |
271 |
| - fsl,tx-deemph-gen1 = <0x2d>; |
272 |
| - fsl,tx-deemph-gen2 = <0xf>; |
273 |
| - clocks = <&pcie0_refclk>; |
274 |
| - status = "okay"; |
275 |
| -}; |
276 |
| - |
277 |
| -&pcie0 { |
278 |
| - pinctrl-names = "default"; |
279 |
| - pinctrl-0 = <&pinctrl_pcie0>; |
280 |
| - reset-gpio = <&gpio3 25 GPIO_ACTIVE_LOW>; |
281 |
| - clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>, |
282 |
| - <&pcie0_refclk>; |
283 |
| - clock-names = "pcie", "pcie_aux", "pcie_bus"; |
284 |
| - assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, |
285 |
| - <&clk IMX8MM_CLK_PCIE1_CTRL>; |
286 |
| - assigned-clock-rates = <10000000>, <250000000>; |
287 |
| - assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>, |
288 |
| - <&clk IMX8MM_SYS_PLL2_250M>; |
289 |
| - vpcie-supply = <®_pcie0>; |
290 |
| - status = "disabled"; |
291 |
| -}; |
292 |
| - |
293 | 252 | &snvs_pwrkey {
|
294 | 253 | status = "okay";
|
295 | 254 | };
|
|
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