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MaxPayne86MaxPayne86
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Portenta-X8: in override, use lpddr4 timing calibrated on portenta-x8 board
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‎meta-arduino-bsp/recipes-bsp/u-boot/u-boot-imx/portenta-x8/lpddr4_timing.c

Lines changed: 73 additions & 68 deletions
Original file line numberDiff line numberDiff line change
@@ -1,60 +1,65 @@
1-
// SPDX-License-Identifier: GPL-2.0+
21
/*
3-
* Copyright 2018-2019 NXP
2+
* Copyright 2019 NXP
3+
*
4+
* SPDX-License-Identifier: GPL-2.0+
45
*
56
* Generated code from MX8M_DDR_tool
7+
*
8+
* Align with uboot version:
9+
* imx_v2019.04_5.4.x and above version
10+
* For imx_v2018.03_4.14.78_1.0.0_ga ~ imx_v2018.04_4.19.35_1.1.0_ga:
11+
* please replace #include <asm/arch/ddr.h> with #include <asm/arch/imx8m_ddr.h>
612
*/
713

814
#include <linux/kernel.h>
915
#include <asm/arch/ddr.h>
1016

1117
struct dram_cfg_param ddr_ddrc_cfg[] = {
12-
/* Initialize DDRC registers */
18+
/** Initialize DDRC registers **/
1319
{ 0x3d400304, 0x1 },
1420
{ 0x3d400030, 0x1 },
1521
{ 0x3d400000, 0xa1080020 },
16-
{ 0x3d400020, 0x223 },
17-
{ 0x3d400024, 0x16e3600 },
18-
{ 0x3d400064, 0x5b00d2 },
22+
{ 0x3d400020, 0x203 },
23+
{ 0x3d400024, 0x3a980 },
24+
{ 0x3d400064, 0x5b0087 },
1925
{ 0x3d4000d0, 0xc00305ba },
2026
{ 0x3d4000d4, 0x940000 },
2127
{ 0x3d4000dc, 0xd4002d },
22-
{ 0x3d4000e0, 0x310000 },
28+
{ 0x3d4000e0, 0xf10000 },
2329
{ 0x3d4000e8, 0x66004d },
2430
{ 0x3d4000ec, 0x16004d },
2531
{ 0x3d400100, 0x191e1920 },
2632
{ 0x3d400104, 0x60630 },
27-
{ 0x3d40010c, 0xb0b000 },
33+
{ 0x3d40010c, 0x80b000 },
2834
{ 0x3d400110, 0xe04080e },
2935
{ 0x3d400114, 0x2040c0c },
3036
{ 0x3d400118, 0x1010007 },
3137
{ 0x3d40011c, 0x401 },
3238
{ 0x3d400130, 0x20600 },
3339
{ 0x3d400134, 0xc100002 },
34-
{ 0x3d400138, 0xd8 },
40+
{ 0x3d400138, 0x8d },
3541
{ 0x3d400144, 0x96004b },
3642
{ 0x3d400180, 0x2ee0017 },
3743
{ 0x3d400184, 0x2605b8e },
3844
{ 0x3d400188, 0x0 },
39-
{ 0x3d400190, 0x497820a },
45+
{ 0x3d400190, 0x49b820a },
4046
{ 0x3d400194, 0x80303 },
41-
{ 0x3d4001b4, 0x170a },
47+
{ 0x3d4001b4, 0x1b0a },
4248
{ 0x3d4001a0, 0xe0400018 },
4349
{ 0x3d4001a4, 0xdf00e4 },
4450
{ 0x3d4001a8, 0x80000000 },
4551
{ 0x3d4001b0, 0x11 },
46-
{ 0x3d4001c0, 0x1 },
47-
{ 0x3d4001c4, 0x0 },
52+
{ 0x3d4001c0, 0x7 },
53+
{ 0x3d4001c4, 0x1 },
4854
{ 0x3d4000f4, 0xc99 },
49-
{ 0x3d400108, 0x70e1617 },
55+
{ 0x3d400108, 0x7101817 },
5056
{ 0x3d400200, 0x1f },
5157
{ 0x3d40020c, 0x0 },
5258
{ 0x3d400210, 0x1f1f },
5359
{ 0x3d400204, 0x80808 },
5460
{ 0x3d400214, 0x7070707 },
5561
{ 0x3d400218, 0x7070707 },
56-
57-
/* performance setting */
62+
{ 0x3d40021c, 0xf0f },
5863
{ 0x3d400250, 0x29001701 },
5964
{ 0x3d400254, 0x2c },
6065
{ 0x3d40025c, 0x4000030 },
@@ -66,14 +71,12 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
6671
{ 0x3d400498, 0x620096 },
6772
{ 0x3d40049c, 0x1100e07 },
6873
{ 0x3d4004a0, 0xc8012c },
69-
70-
/* P1: 400mts */
71-
{ 0x3d402020, 0x21 },
72-
{ 0x3d402024, 0x30d400 },
74+
{ 0x3d402020, 0x1 },
75+
{ 0x3d402024, 0x7d00 },
7376
{ 0x3d402050, 0x20d040 },
74-
{ 0x3d402064, 0xc001c },
77+
{ 0x3d402064, 0xc0012 },
7578
{ 0x3d4020dc, 0x840000 },
76-
{ 0x3d4020e0, 0x310000 },
79+
{ 0x3d4020e0, 0xf10000 },
7780
{ 0x3d4020e8, 0x66004d },
7881
{ 0x3d4020ec, 0x16004d },
7982
{ 0x3d402100, 0xa040305 },
@@ -86,20 +89,19 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
8689
{ 0x3d40211c, 0x301 },
8790
{ 0x3d402130, 0x20300 },
8891
{ 0x3d402134, 0xa100002 },
89-
{ 0x3d402138, 0x1d },
92+
{ 0x3d402138, 0x13 },
9093
{ 0x3d402144, 0x14000a },
9194
{ 0x3d402180, 0x640004 },
9295
{ 0x3d402190, 0x3818200 },
9396
{ 0x3d402194, 0x80303 },
9497
{ 0x3d4021b4, 0x100 },
95-
96-
/* p2: 100mts */
97-
{ 0x3d403020, 0x21 },
98-
{ 0x3d403024, 0xc3500 },
98+
{ 0x3d4020f4, 0xc99 },
99+
{ 0x3d403020, 0x1 },
100+
{ 0x3d403024, 0x1f40 },
99101
{ 0x3d403050, 0x20d040 },
100-
{ 0x3d403064, 0x30007 },
102+
{ 0x3d403064, 0x30005 },
101103
{ 0x3d4030dc, 0x840000 },
102-
{ 0x3d4030e0, 0x310000 },
104+
{ 0x3d4030e0, 0xf10000 },
103105
{ 0x3d4030e8, 0x66004d },
104106
{ 0x3d4030ec, 0x16004d },
105107
{ 0x3d403100, 0xa010102 },
@@ -112,14 +114,13 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
112114
{ 0x3d40311c, 0x301 },
113115
{ 0x3d403130, 0x20300 },
114116
{ 0x3d403134, 0xa100002 },
115-
{ 0x3d403138, 0x8 },
117+
{ 0x3d403138, 0x5 },
116118
{ 0x3d403144, 0x50003 },
117119
{ 0x3d403180, 0x190004 },
118120
{ 0x3d403190, 0x3818200 },
119121
{ 0x3d403194, 0x80303 },
120122
{ 0x3d4031b4, 0x100 },
121-
122-
/* default boot point */
123+
{ 0x3d4030f4, 0xc99 },
123124
{ 0x3d400028, 0x0 },
124125
};
125126

@@ -135,20 +136,20 @@ struct dram_cfg_param ddr_ddrphy_cfg[] = {
135136
{ 0x100a7, 0x7 },
136137
{ 0x110a0, 0x0 },
137138
{ 0x110a1, 0x1 },
138-
{ 0x110a2, 0x3 },
139-
{ 0x110a3, 0x4 },
140-
{ 0x110a4, 0x5 },
141-
{ 0x110a5, 0x2 },
142-
{ 0x110a6, 0x7 },
143-
{ 0x110a7, 0x6 },
139+
{ 0x110a2, 0x2 },
140+
{ 0x110a3, 0x3 },
141+
{ 0x110a4, 0x4 },
142+
{ 0x110a5, 0x5 },
143+
{ 0x110a6, 0x6 },
144+
{ 0x110a7, 0x7 },
144145
{ 0x120a0, 0x0 },
145146
{ 0x120a1, 0x1 },
146-
{ 0x120a2, 0x3 },
147-
{ 0x120a3, 0x2 },
148-
{ 0x120a4, 0x5 },
149-
{ 0x120a5, 0x4 },
150-
{ 0x120a6, 0x7 },
151-
{ 0x120a7, 0x6 },
147+
{ 0x120a2, 0x2 },
148+
{ 0x120a3, 0x3 },
149+
{ 0x120a4, 0x4 },
150+
{ 0x120a5, 0x5 },
151+
{ 0x120a6, 0x6 },
152+
{ 0x120a7, 0x7 },
152153
{ 0x130a0, 0x0 },
153154
{ 0x130a1, 0x1 },
154155
{ 0x130a2, 0x2 },
@@ -207,8 +208,8 @@ struct dram_cfg_param ddr_ddrphy_cfg[] = {
207208
{ 0x220024, 0x1ab },
208209
{ 0x2003a, 0x0 },
209210
{ 0x20056, 0x3 },
210-
{ 0x120056, 0xa },
211-
{ 0x220056, 0xa },
211+
{ 0x120056, 0x3 },
212+
{ 0x220056, 0x3 },
212213
{ 0x1004d, 0xe00 },
213214
{ 0x1014d, 0xe00 },
214215
{ 0x1104d, 0xe00 },
@@ -316,9 +317,9 @@ struct dram_cfg_param ddr_ddrphy_cfg[] = {
316317
{ 0x200f6, 0x0 },
317318
{ 0x200f7, 0xf000 },
318319
{ 0x20025, 0x0 },
319-
{ 0x2002d, 0x0 },
320-
{ 0x12002d, 0x0 },
321-
{ 0x22002d, 0x0 },
320+
{ 0x2002d, 0x1 },
321+
{ 0x12002d, 0x1 },
322+
{ 0x22002d, 0x1 },
322323
{ 0x200c7, 0x21 },
323324
{ 0x1200c7, 0x21 },
324325
{ 0x2200c7, 0x21 },
@@ -1061,32 +1062,33 @@ struct dram_cfg_param ddr_fsp0_cfg[] = {
10611062
{ 0x5400b, 0x2 },
10621063
{ 0x54012, 0x110 },
10631064
{ 0x54019, 0x2dd4 },
1064-
{ 0x5401a, 0x31 },
1065+
{ 0x5401a, 0xf1 },
10651066
{ 0x5401b, 0x4d66 },
10661067
{ 0x5401c, 0x4d00 },
10671068
{ 0x5401e, 0x16 },
10681069
{ 0x5401f, 0x2dd4 },
1069-
{ 0x54020, 0x31 },
1070+
{ 0x54020, 0xf1 },
10701071
{ 0x54021, 0x4d66 },
10711072
{ 0x54022, 0x4d00 },
10721073
{ 0x54024, 0x16 },
10731074
{ 0x5402b, 0x1000 },
10741075
{ 0x5402c, 0x1 },
10751076
{ 0x54032, 0xd400 },
1076-
{ 0x54033, 0x312d },
1077+
{ 0x54033, 0xf12d },
10771078
{ 0x54034, 0x6600 },
10781079
{ 0x54035, 0x4d },
10791080
{ 0x54036, 0x4d },
10801081
{ 0x54037, 0x1600 },
10811082
{ 0x54038, 0xd400 },
1082-
{ 0x54039, 0x312d },
1083+
{ 0x54039, 0xf12d },
10831084
{ 0x5403a, 0x6600 },
10841085
{ 0x5403b, 0x4d },
10851086
{ 0x5403c, 0x4d },
10861087
{ 0x5403d, 0x1600 },
10871088
{ 0xd0000, 0x1 },
10881089
};
10891090

1091+
10901092
/* P1 message block paremeter for training firmware */
10911093
struct dram_cfg_param ddr_fsp1_cfg[] = {
10921094
{ 0xd0000, 0x0 },
@@ -1100,32 +1102,33 @@ struct dram_cfg_param ddr_fsp1_cfg[] = {
11001102
{ 0x5400b, 0x2 },
11011103
{ 0x54012, 0x110 },
11021104
{ 0x54019, 0x84 },
1103-
{ 0x5401a, 0x31 },
1105+
{ 0x5401a, 0xf1 },
11041106
{ 0x5401b, 0x4d66 },
11051107
{ 0x5401c, 0x4d00 },
11061108
{ 0x5401e, 0x16 },
11071109
{ 0x5401f, 0x84 },
1108-
{ 0x54020, 0x31 },
1110+
{ 0x54020, 0xf1 },
11091111
{ 0x54021, 0x4d66 },
11101112
{ 0x54022, 0x4d00 },
11111113
{ 0x54024, 0x16 },
11121114
{ 0x5402b, 0x1000 },
11131115
{ 0x5402c, 0x1 },
11141116
{ 0x54032, 0x8400 },
1115-
{ 0x54033, 0x3100 },
1117+
{ 0x54033, 0xf100 },
11161118
{ 0x54034, 0x6600 },
11171119
{ 0x54035, 0x4d },
11181120
{ 0x54036, 0x4d },
11191121
{ 0x54037, 0x1600 },
11201122
{ 0x54038, 0x8400 },
1121-
{ 0x54039, 0x3100 },
1123+
{ 0x54039, 0xf100 },
11221124
{ 0x5403a, 0x6600 },
11231125
{ 0x5403b, 0x4d },
11241126
{ 0x5403c, 0x4d },
11251127
{ 0x5403d, 0x1600 },
11261128
{ 0xd0000, 0x1 },
11271129
};
11281130

1131+
11291132
/* P2 message block paremeter for training firmware */
11301133
struct dram_cfg_param ddr_fsp2_cfg[] = {
11311134
{ 0xd0000, 0x0 },
@@ -1139,32 +1142,33 @@ struct dram_cfg_param ddr_fsp2_cfg[] = {
11391142
{ 0x5400b, 0x2 },
11401143
{ 0x54012, 0x110 },
11411144
{ 0x54019, 0x84 },
1142-
{ 0x5401a, 0x31 },
1145+
{ 0x5401a, 0xf1 },
11431146
{ 0x5401b, 0x4d66 },
11441147
{ 0x5401c, 0x4d00 },
11451148
{ 0x5401e, 0x16 },
11461149
{ 0x5401f, 0x84 },
1147-
{ 0x54020, 0x31 },
1150+
{ 0x54020, 0xf1 },
11481151
{ 0x54021, 0x4d66 },
11491152
{ 0x54022, 0x4d00 },
11501153
{ 0x54024, 0x16 },
11511154
{ 0x5402b, 0x1000 },
11521155
{ 0x5402c, 0x1 },
11531156
{ 0x54032, 0x8400 },
1154-
{ 0x54033, 0x3100 },
1157+
{ 0x54033, 0xf100 },
11551158
{ 0x54034, 0x6600 },
11561159
{ 0x54035, 0x4d },
11571160
{ 0x54036, 0x4d },
11581161
{ 0x54037, 0x1600 },
11591162
{ 0x54038, 0x8400 },
1160-
{ 0x54039, 0x3100 },
1163+
{ 0x54039, 0xf100 },
11611164
{ 0x5403a, 0x6600 },
11621165
{ 0x5403b, 0x4d },
11631166
{ 0x5403c, 0x4d },
11641167
{ 0x5403d, 0x1600 },
11651168
{ 0xd0000, 0x1 },
11661169
};
11671170

1171+
11681172
/* P0 2D message block paremeter for training firmware */
11691173
struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
11701174
{ 0xd0000, 0x0 },
@@ -1179,25 +1183,25 @@ struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
11791183
{ 0x54010, 0x1f7f },
11801184
{ 0x54012, 0x110 },
11811185
{ 0x54019, 0x2dd4 },
1182-
{ 0x5401a, 0x31 },
1186+
{ 0x5401a, 0xf1 },
11831187
{ 0x5401b, 0x4d66 },
11841188
{ 0x5401c, 0x4d00 },
11851189
{ 0x5401e, 0x16 },
11861190
{ 0x5401f, 0x2dd4 },
1187-
{ 0x54020, 0x31 },
1191+
{ 0x54020, 0xf1 },
11881192
{ 0x54021, 0x4d66 },
11891193
{ 0x54022, 0x4d00 },
11901194
{ 0x54024, 0x16 },
11911195
{ 0x5402b, 0x1000 },
11921196
{ 0x5402c, 0x1 },
11931197
{ 0x54032, 0xd400 },
1194-
{ 0x54033, 0x312d },
1198+
{ 0x54033, 0xf12d },
11951199
{ 0x54034, 0x6600 },
11961200
{ 0x54035, 0x4d },
11971201
{ 0x54036, 0x4d },
11981202
{ 0x54037, 0x1600 },
11991203
{ 0x54038, 0xd400 },
1200-
{ 0x54039, 0x312d },
1204+
{ 0x54039, 0xf12d },
12011205
{ 0x5403a, 0x6600 },
12021206
{ 0x5403b, 0x4d },
12031207
{ 0x5403c, 0x4d },
@@ -1695,15 +1699,15 @@ struct dram_cfg_param ddr_phy_pie[] = {
16951699
{ 0x400d6, 0x20a },
16961700
{ 0x400d7, 0x20b },
16971701
{ 0x2003a, 0x2 },
1698-
{ 0x2000b, 0x5d },
1702+
{ 0x2000b, 0x34b },
16991703
{ 0x2000c, 0xbb },
17001704
{ 0x2000d, 0x753 },
17011705
{ 0x2000e, 0x2c },
1702-
{ 0x12000b, 0xc },
1706+
{ 0x12000b, 0x70 },
17031707
{ 0x12000c, 0x19 },
17041708
{ 0x12000d, 0xfa },
17051709
{ 0x12000e, 0x10 },
1706-
{ 0x22000b, 0x3 },
1710+
{ 0x22000b, 0x1c },
17071711
{ 0x22000c, 0x6 },
17081712
{ 0x22000d, 0x3e },
17091713
{ 0x22000e, 0x10 },
@@ -1846,3 +1850,4 @@ struct dram_timing_info dram_timing = {
18461850
.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
18471851
.fsp_table = { 3000, 400, 100, },
18481852
};
1853+

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