|
39 | 39 | };
|
40 | 40 | };
|
41 | 41 |
|
42 |
| -&{/soc@0} { |
43 |
| - u-boot,dm-pre-reloc; |
| 42 | +&aips4 { |
44 | 43 | u-boot,dm-spl;
|
45 | 44 | };
|
46 | 45 |
|
47 |
| -&A53_0 { |
48 |
| - /delete-property/ cpu-idle-states; |
| 46 | +®_usdhc2_vmmc { |
| 47 | + u-boot,off-on-delay-us = <20000>; |
| 48 | + u-boot,dm-spl; |
49 | 49 | };
|
50 | 50 |
|
51 |
| -&A53_1 { |
52 |
| - /delete-property/ cpu-idle-states; |
| 51 | +&pinctrl_reg_usdhc2_vmmc { |
| 52 | + u-boot,dm-spl; |
53 | 53 | };
|
54 | 54 |
|
55 |
| -&A53_2 { |
56 |
| - /delete-property/ cpu-idle-states; |
| 55 | +&pinctrl_uart2 { |
| 56 | + u-boot,dm-spl; |
57 | 57 | };
|
58 | 58 |
|
59 |
| -&A53_3 { |
60 |
| - /delete-property/ cpu-idle-states; |
| 59 | +&pinctrl_usdhc2_gpio { |
| 60 | + u-boot,dm-spl; |
61 | 61 | };
|
62 |
| -&i2c2 { |
| 62 | + |
| 63 | +&pinctrl_usdhc2 { |
63 | 64 | u-boot,dm-spl;
|
64 | 65 | };
|
| 66 | + |
| 67 | +&pinctrl_usdhc3 { |
| 68 | + u-boot,dm-spl; |
| 69 | +}; |
| 70 | + |
65 | 71 | &gpio1 {
|
66 | 72 | u-boot,dm-spl;
|
67 | 73 | };
|
|
82 | 88 | u-boot,dm-spl;
|
83 | 89 | };
|
84 | 90 |
|
| 91 | +&uart2 { |
| 92 | + u-boot,dm-spl; |
| 93 | +}; |
| 94 | + |
| 95 | +&crypto { |
| 96 | + u-boot,dm-spl; |
| 97 | +}; |
| 98 | + |
| 99 | +&sec_jr0 { |
| 100 | + u-boot,dm-spl; |
| 101 | +}; |
| 102 | + |
| 103 | +&sec_jr1 { |
| 104 | + u-boot,dm-spl; |
| 105 | +}; |
| 106 | + |
| 107 | +&sec_jr2 { |
| 108 | + u-boot,dm-spl; |
| 109 | +}; |
| 110 | + |
| 111 | +&usbmisc1 { |
| 112 | + u-boot,dm-spl; |
| 113 | +}; |
| 114 | + |
| 115 | +&usbphynop1 { |
| 116 | + u-boot,dm-spl; |
| 117 | +}; |
| 118 | + |
| 119 | +&usbotg1 { |
| 120 | + u-boot,dm-spl; |
| 121 | +}; |
| 122 | + |
| 123 | +&usdhc1 { |
| 124 | + u-boot,dm-spl; |
| 125 | + assigned-clocks = <&clk IMX8MM_CLK_USDHC1>; |
| 126 | + assigned-clock-rates = <400000000>; |
| 127 | + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_400M>; |
| 128 | +}; |
| 129 | + |
85 | 130 | &usdhc2 {
|
86 | 131 | u-boot,dm-spl;
|
87 | 132 | sd-uhs-sdr104;
|
|
105 | 150 | u-boot,dm-spl;
|
106 | 151 | };
|
107 | 152 |
|
108 |
| -&{/soc@0/bus@30800000/i2c@30a30000/pmic@4b} { |
| 153 | +&{/soc@0/bus@30800000/i2c@30a20000/pca9450@25} { |
109 | 154 | u-boot,dm-spl;
|
110 | 155 | };
|
111 | 156 |
|
112 |
| -&{/soc@0/bus@30800000/i2c@30a30000/pmic@4b/regulators} { |
| 157 | +&{/soc@0/bus@30800000/i2c@30a20000/pca9450@25/regulators} { |
113 | 158 | u-boot,dm-spl;
|
114 | 159 | };
|
115 | 160 |
|
116 |
| - |
117 | 161 | &pinctrl_i2c1 {
|
118 | 162 | u-boot,dm-spl;
|
119 | 163 | };
|
|
122 | 166 | u-boot,dm-spl;
|
123 | 167 | };
|
124 | 168 |
|
| 169 | +&pinctrl_wdog { |
| 170 | + u-boot,dm-spl; |
| 171 | +}; |
| 172 | + |
125 | 173 | &fec1 {
|
126 |
| - phy-reset-gpios = <&gpio3 6 GPIO_ACTIVE_LOW>; |
127 |
| - phy-reset-duration = <100>; |
128 |
| - phy-reset-post-delay = <1>; |
| 174 | + phy-reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; |
| 175 | + phy-reset-duration = <15>; |
| 176 | + phy-reset-post-delay = <100>; |
129 | 177 | };
|
130 | 178 |
|
131 |
| -&wdog1 { |
132 |
| - u-boot,dm-spl; |
| 179 | +ðphy0 { |
| 180 | + vddio0: vddio-regulator { |
| 181 | + regulator-name = "VDDIO"; |
| 182 | + regulator-min-microvolt = <1800000>; |
| 183 | + regulator-max-microvolt = <1800000>; |
| 184 | + }; |
133 | 185 | };
|
134 | 186 |
|
135 |
| -&flexspi { |
136 |
| - assigned-clock-rates = <100000000>; |
137 |
| - assigned-clocks = <&clk IMX8MM_CLK_QSPI>; |
138 |
| - assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>; |
| 187 | +&wdog1 { |
| 188 | + u-boot,dm-spl; |
139 | 189 | };
|
140 | 190 |
|
141 |
| -&lcdif { |
142 |
| - enable_polarity_low; |
143 |
| - /delete-property/ assigned-clocks; |
144 |
| - /delete-property/ assigned-clock-parents; |
145 |
| - /delete-property/ assigned-clock-rates; |
| 191 | +&usbotg1 { |
| 192 | + status = "okay"; |
| 193 | + extcon = <&ptn5110>; |
146 | 194 | };
|
147 | 195 |
|
148 | 196 | &mipi_dsi {
|
|
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